Stmicroelectronics (research & Development) Limited

Stmicroelectronics R&d Limited

Cirrus Logic Inc.

Ecole Polytechnique Federale De Lausanne

Dialog Semiconductor (uk) Limited

The University of Edinburgh

Dialog Semiconductor Gmbh

Justin Richardson

Robert K Henderson

John L Melanson

Ramin Zanbaghi

Aleksey Sergeyevich Khenkin

Lingli Zhang

David Patten

Edoardo Charbon

Donald Baxter

Cristiano Niclass

Andrew John Myles

Keith Findlater

Lindsay Grant

Marek Gersbach

Wei Xu

Michael Robinson

Mairead Kelly

A packaged semiconductor die may include a package terminal array comprising a plurality of terminals, wherein a spacing between the plurality of terminals of the ball grid array is less than 0.5 mm. First and second high-voltage circuits of the die may output a differential signal to a first and second terminal that may exceed 15 volts, in which the first high-voltage circuit and the second high-voltage circuit are positioned symmetrically around an axis and in which the first terminal and the second terminal are located at an edge of the package terminal array. A low-voltage circuit may be coupled to a third terminal and positioned between the first high-voltage circuit and the second high-voltage circuit, wherein the low-voltage circuit comprises circuitry organized in columns aligned along an axis and having a width defined by a fraction of the terminal spacing pitch.

Symmetric layout for high-voltage amplifier

A system for sensing an electrical quantity may include a sensing stage configured to sense the electrical quantity and generate a sense signal indicative of the electrical quantity, wherein the electrical quantity is indicative of an electrical signal generated by a Class-DG amplifier configured to drive a load wherein the Class-DG amplifier has multiple signal-level common modes and a common-mode compensator configured to compensate for changes to a common-mode voltage of a differential supply voltage of the driver occurring when switching between signal-level common modes of the Class-DG amplifier.

Common-mode compensation in a multi-level pulse-width modulation system

An image sensor IC may have a non-volatile memory for several functions. The functions may include storing control parameters for a camera autofocus module, part tracking data, and data for defect correction or color science. The non-volatile memory can in particular be an antifuse non-volatile memory, which may not need special light shielding.

Memory-enhanced image sensor

A capacitance reduction circuit retains a conversion digital code of a previous sampling of an input signal of a delta-sigma modulated ADC and compares a set of least significant data bits and most significant bits of the conversion digital code to a least significant and a most significant boundary codes. When the least significant bits of the conversion digital code are less than or equal to the least significant boundary code or when the most significant bits of the conversion digital code are greater than or equal to the most significant boundary code, the capacitance reduction circuitry generates a capacitance reduction enable/disable code applied to multiple summation-quantization circuits to enable or disable groups of the multiple summation-quantization circuits bits to reduce capacitive loading of the outputs of delta-sigma modulator and an input signal to improve the total harmonic distortion and noise.

Flash converter capacitance reduction method

A photodetector includes a photodiode and output circuitry coupled to the photodiode. The photodetector is configurable for operation in at least two modes. A first configurable mode operates the photodetector as an integrating sensor. In this first mode, a bias voltage across the photodiode is set below the breakdown voltage of the photodiode and the output circuitry is configured to read an analog integration output voltage from the photodiode. A second configurable mode operates the photodetector as a single photon avalanche detector. In this second mode, the bias voltage across the photodiode is set above the breakdown voltage of the photodiode and the output circuitry is configured to read an avalanche output voltage.

Multi-mode photodetector

A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.

Single photon avalanche diodes

In a solid state image sensor having a pixel array, a first frame is imaged using varying exposure times in a series of zones. The exposure time for a subsequent frame is selected from the results of the first frame, The exposure times are controlled in a rolling blade manner by controlling the number of lines between reset and readout. The sensor is particularly suited to use in bar code readers.

Method and apparatus for exposure level setting in machine vision systems

An image sensor may include a shared memory resource, which can be selectively used by a digital filter for image scaling or by a defect correction circuit.

Method of operating an image sensor

An image sensor may have a power supply voltage regulator controlled by a feedback loop. The feedback signal may be derived by applying the supply voltage at a point distant from the voltage regulator to an analog-to-digital converter (ADC) which may be a spare channel of an ADC provided for the output of the pixel array. The digital feedback loop may be controlled via a chip IC bus.

Image sensor power supply

A semiconductor device includes a semiconductor substrate, a photon avalanche detector in the semiconductor substrate. The photon avalanche detector includes an anode of a first conductivity type and a cathode of a second conductivity type. A guard ring is in the semiconductor substrate and at least partially surrounds the photon avalanche detector. A passivation layer of the first conductivity type is in contact with the guard ring to reduce an electric field at an edge of the photon avalanche detector.

Single photon detector and associated methods for making the same

An image sensor power distribution arrangement includes a sensing portion having a first contact at a first edge thereof and a second contact at a second edge thereof, and a control portion. A first power supply supplies power to the sensing portion via the first contact. A second power supply supplies power to the sensing portion via the second contact, and to the control portion.

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Edinburgh, United Kingdom

Justin Richardson