International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Emc IP Holding Company LLC

Emc Corporation

Justin Potok Bandholz

Pravin S Patel

Philip Louis Weinstein

William Joseph Piazza

Clifton Ehrich Kerr

Joseph Eric Maxwell

William Gabriel Pagan

Kevin Michael Reinberg

Christopher Collier West

Andrew S Heinzmann

Zachary Benson Durham

Bhyrav M Mutnury

Moises Cases

Nam Huu Pham

Jonathan Randall Hinkle

Kevin S D Vernon

Erdem Matoglu

Brian Michael Kerrigan

Ralph M Begun

Edward John McNulty

Robert J Christopher

Peter Robert Seidel

Kevin S Vernon

Fernando Aramis Lopez

Jimmy Grant Foster, Sr

Martin Joseph Crippen

James Joseph Parsonese

Robert P Wierzbicki

Ralph C Frangioso, Jr

Daniel N De Araujo

Bradley Donald Herrman

Nickolas John Gruendler

Marcus Alan Baker

Michael Sean Gregoire

Jiabing Li

Bradley D Herman

Thomas D Pahel

Phillip L Weinstein

James A O'Connor

Paul Theodore Artman

Sumeet Kochar

Thomas M Brey

Patrick M Bland

Bruce James Wilkie

Mickey Steven Felton

Alfredo Aldereguia

James Edward Hughes

W Brian Cunningham

Jeffery Michael Franke

Tony Carl Sass

Joseph Edward Bolan

Keith Clifford Johnson

David John Jensen

John K Langgood

Jeffrey Buchanan Williams

Thomas Dixon Pahel, Jr

Ivan R Zapata

Nagananda Chumbalkar

Jerry Don Ackaret

Brian A Baker

Wilson Earl Smith

Bay Van Nguyen

Derek Robertson

William James Sommerville

John M Sheplock

Brian E Bigelow

Timothy Paul Hiteshew

Christopher Lee Durham

Kevin M Cash

Matthew S Michaels

William H Cox, Jr

David L Cowell

Joseph M Jacobs

Pravin Patal

John Frank Nations, Jr

Richard Jesse Muse

Devarshi S Patel

An apparatus can include a processor; a controller; a data bus connector; a multiplexer operatively coupled to the data bus connector where the multiplexer includes a controller coupled state operatively coupled to the controller and a processor coupled state operatively coupled to the processor; and circuitry that responds to a signal received via the data bus connector to determine the coupled state of the multiplexer as being one of the controller coupled state and the processor coupled state. Various other apparatuses, systems, methods, etc., are also disclosed.

Data bus host and controller switch

System, computer implemented method and computer program product for preparing and navigating a query tree including a plurality of query nodes and informational nodes. Each query node is associated with a prompt, branching criteria and keywords. A current query node provides a prompt to a user and a user response is received and analyzed to identify branching criteria and keywords from the user response. The method navigates to another node in the query tree in consideration of the branching criteria received in the user response and a comparison between the keywords received in the user response and the keywords associated with the query nodes. The comparison may validate navigation to a destination node corresponding to the branching criteria or the comparison may indicate incorrect navigation of the query tree. Corrective navigation can be implemented in various ways based upon the keywords received in the user response.

Query tree navigation

In one aspect, a device includes at least one processor, storage, a power supply unit (PSU) interlace which connects to a PSU and receives power from the PSU, and a power module (PM) including a power in interface for receiving power from at least one computer and a power out interface for providing power to at least one computer.

Supply of power from one device to another device

An integrated circuit (IC) that includes a semiconductor die in an IC package. The semiconductor die includes an electrical endpoint. The IC also includes a pad affixed to the semiconductor die. The pad is characterized by a capacitance and is coupled to the electrical endpoint. The IC also includes a bond wire coupling the pad to an IC package pin. The bond wire is an inductor characterized by an inductance. The inductance is configured to decrease signal degradation caused by the capacitance of the pad on electrical signals transmitted between the pin and the electrical endpoint of the semiconductor die.

Integrated circuit with inductive bond wires

A computing system includes a low-profile chassis a motherboard disposed therein and at least one full-size circuit board coupled to the motherboard within the chassis. A method and another computing system are disclosed.

Universal mezzanine connector

Method and computer program product for using an RFID antenna of a cooking appliance to read a plurality of cooking instruction sets from a single RFID tag associated with a food product that is positioned to be cooked by the cooking appliance. The cooking appliance selects one of the plurality of cooking instruction sets that the cooking appliance is capable of performing. Furthermore, the cooking appliance may then automatically cook the food product by controlling the cooking appliance according to the selected cooking instruction set. The selection of a cooking instruction set may consider the temperature of the food product or a determination whether the food product is frozen. Alternatively, cooking appliance settings may be interpolated between two cooking instruction sets or calculated on the basis of physical property information about the food product.

Operating an appliance based on cooking instructions embedded in an RFID product tag

Mapping computers and ports of power distribution units in a data center, the data center including a plurality of computers and a data center management server, each computer in the data center connected for power to one of a plurality of power distribution unit ('PDU') ports of a PDU, each PDU connected through the communications module and a data communications network to the data center management server, including generating, by a power modulating module of a computer, a power consumption signal in the PDU, the power consumption signal encoding a unique identification of the computer; demodulating, by the PDU, the power consumption signal, including retrieving from the signal the unique identification of the computer; and reporting, by the PDU to the data center management server, an association of the unique identification of the computer and a PDU port.

Mapping computers and ports of power distribution units in a data center

An IT chassis, configured to house IT componentry, includes a forward portion having a forward portion width and a rearward portion having a rearward portion width that is narrower than the forward portion width. A first side of the rearward portion is configured to engage a first slide assembly having a first slide width. A second side of the rearward portion is configured to engage a second slide assembly having a second slide width. The sum of the rearward portion width, the first slide width and the second slide width is substantially equal to the forward portion width.

Rack-mountable IT device

Method and systems are disclosed for increasing the number of ranks supported in a memory system. In one embodiment, a plurality of predefined subsets of memory chips on a memory module is selected. A chip select signal uniquely identifying the selected subset of memory chips is generated. The chip select signal is encoded as a multi-bit word having a bit width that is less than the number of predefined subsets of memory chips. Each bit of the encoded chip select signal is transmitted along a separate chip select line. The transmitted chip select signal is decoded to determine the identity of the selected subset of memory chips. The selected subset of memory chips identified by the decoded chip select signal are read or written.

Encoded chip select for supporting more memory ranks

A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

DIMM riser care with an angled DIMM socket and a straddle mount DIMM socket

Computer memory subsystems are disclosed for enhancing signal quality that include: one or more memory modules; a memory bus; and a memory controller connected to the memory modules through the memory bus, the memory controller including a reception buffer connected to the memory bus, the reception buffer capable of receiving an input signal from one of the memory modules, the memory controller including a reception characteristics table capable of storing reception characteristics for each of the memory modules connected to the memory controller, the memory controller including an equalizer connected to the reception buffer and the reception characteristics table, the equalizer capable of equalizing the received input signal in dependence upon the reception characteristics for the memory module from which the input signal was received, and the memory controller including memory controller logic connected to the equalizer, the memory controller logic capable of processing the equalized input signal.

Computer memory subsystem for enhancing signal quality

Methods, apparatus, and products are disclosed for implementing a redundant array of inexpensive drives ('RAID') with an external RAID controller and hard disk drives from separate computers, including configuring by the external RAID controller a RAID array, the RAID array comprising hard disk drives from the separate computers, the external RAID controller comprising a hardware RAID controller installed externally with respect to the separate computers, and storing, by one or more of the separate computers through the external RAID controller, computer data on the RAID array.

Implementing a redundant array of inexpensive drives

A computer-implemented method, and computer program product, for switching the I/O protocol of a multiprotocol I/O adapter while a computer system including the multiprotocol I/O adapter is running. The method comprises running a multiprotocol I/O adapter using a first I/O protocol while a computer system including the multiprotocol I/O adapter is running, and logically removing the adapter from the system while the computer system continues running. The multiprotocol I/O adapter is then caused to switch to a second I/O protocol while the adapter is logically removed and the computer system continues running. While the computer system still continues to run, the multiprotocol I/O adapter is restarted. After restarting, the multiprotocol I/O adapter runs using the second I/O protocol while the computer system continues running. In a virtualization environment, the method allows a multiprotocol I/O adapter to meet the varying I/O requirements of one or more virtual machines.

Automated network configuration in a dynamic virtual environment

In a memory system, a spare error correction bit is produced by processing data to be stored in sufficiently large chunks that the number of error correction bits required to protect each chunk are fewer than the available error correction signal lines on a memory bus and storage device. The spare bit is then used for an inversion bit in a parallel data bus inversion scheme, wherein data is selectively inverted to minimize bus switching. The transmission of data and error correction bits are spread over multiple phases, wherein parallel data bus inversion is applied to each phase. Alternatively, the transmission of data and error correction bits may be transmitted and stored in a single transaction. In either case, the spare bit is transmitted on a conventional memory bus and stored in a conventional memory module along with data and error correction bits.

Data bus inversion using spare error correction bits

Growing community of inventors

Cary, NC, United States of America

Justin Potok Bandholz