Lam Research Corporation

Justin Oberst

Bryan L Buckalew

Stephen J Banik

Steven T Mayer

Thomas Anand Ponnuswamy

Kari Thorkelsson

Robert Rash

Aaron Berke

James Isaac Fortner

Stephen J Banik, Ii

Direct copper-copper bonding at low temperatures is achieved by electroplating copper features on a substrate followed by electroplanarizing the copper features. The copper features are electroplated on the substrate under conditions so that nanotwinned copper structures are formed. Electroplanarizing the copper features is performed by anodically biasing the substrate and contacting the copper features with an electrolyte so that copper is electrochemically removed. Such electrochemical removal is performed in a manner so that roughness is reduced in the copper features and substantial coplanarity is achieved among the copper features. Copper features having nanotwinned copper structures, reduced roughness, and better coplanarity enable direct copper-copper bonding at low temperatures.

Low temperature direct copper-copper bonding

Sequential electrodeposition of metals into through-mask features on a semiconductor substrate is conducted such as to reduce the deleterious consequences of lipseal's pressure onto the mask material. In a first electroplating step, a first metal (e.g., nickel) is electrodeposited using a lipseal that has an innermost point of contact with the semiconductor substrate at a first distance from the edge of the substrate. In a second electroplating step, a second metal (e.g., tin) is electrodeposited using a lipseal that has an innermost point of contact with the semiconductor substrate at a greater distance from the edge of the substrate than the first distance. This allows to at least partially shift the lipseal pressure from a point that could have been damaged during the first electrodeposition step and to shield from electrolyte any cracks that might have formed in the mask material during the first electroplating step.

Lipseal edge exclusion engineering to maintain material integrity at wafer edge

In one example, a method for redistribution layer (RDL) process is described. A substrate is provided. A dielectric layer is deposited on top of the substrate. The dielectric layer is patterned. A barrier and copper seed layer are deposited on top of the dielectric layer. A photoresist layer is applied on top of the barrier and copper seed layer. The photoresist layer is patterned to correspond with the dielectric layer pattern. Copper is electrodepositing in the patterned regions exposed by the photoresist layer. The photoresist layer is removed. The copper and seed barrier are etched.

Alternative integration for redistribution layer process

Various embodiments described herein relate to methods and apparatus for electroplating material onto a semiconductor substrate. In some cases, one or more membrane may be provided in contact with an ionically resistive element to minimize the degree to which electrolyte passes backwards from a cross flow manifold, through the ionically resistive element, and into an ionically resistive element manifold during electroplating. The membrane may be designed to route electrolyte in a desired manner in some embodiments. In these or other cases, one or more baffles may be provided in the ionically resistive element manifold to reduce the degree to which electrolyte is able to bypass the cross flow manifold by flowing back through the ionically resistive element and across the electroplating cell within the ionically resistive element manifold. These techniques can be used to improve the uniformity of electroplating results.

Methods and apparatus for flow isolation and focusing during electroplating

Systems and methods for achieving uniformity across a redistribution layer are described. One of the methods includes patterning a photoresist layer over a substrate. The patterning defines a region for a conductive line and a via disposed below the region for the conductive line. The method further includes depositing a conductive material in between the patterned photoresist layer, such that the conductive material fills the via and the region for the conductive line. The depositing causes an overgrowth of conductive material of the conductive line to form a bump of the conductive material over the via. The method also includes planarizing a top surface of the conductive line while maintaining the patterned photoresist layer present over the substrate. The planarizing is facilitated by exerting a horizontal shear force over the conductive line and the bump. The planarizing is performed to flatten the bump.

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Beaverton, OR, United States of America

Justin Oberst