Hittite Microwave Corporation

Psion Teklogix Systems Inc.

Justin L Fortier

Gordon John Allan

Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal. When the control circuit determines that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch. After the selected reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock.

Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock

Provided herein are apparatus and methods for fast charge pump holdover on signal interruption. In certain configurations, a clock generator system includes a phase-locked loop (PLL), a fast detect circuit, and a switch electrically coupled to an input of the PLL's loop filter. The fast detect circuit relatively quickly detects when an input signal to the PLL is lost. The fast detect circuit can quickly detect the loss of phase lock and can place the PLL into a holdover such that the frequency of a clock signal generated by the PLL remains within an acceptable range.

Apparatus and methods for fast charge pump holdover on signal interruption

The method and apparatus for processing pixel output signals from column lines in an imager having an array of pixels in rows and columns uses a sigma-delta type analog-to-digital converter to convert the output signals on each column line to digital signals and feeding them to a digital signal processor. The converter is monitored to stop sampling of a pixel with the detection of pixel saturation, which is carried out by counting a predetermined number of consecutive zeros in the converted signal. In addition, the next pixel in a column may be controlled to be read with the saturation of the previous pixel, and the next row of pixels may be controlled to be read with the saturation of the pixels in the previous row. Further, sets of a predetermined number of converter output samples are condensed by a decimator into binary numbers of predetermined bit length. The outputs of the decimators may be fed directly to the digital signal processor or they may be multiplexed to provide one or more inputs to the digital signal processor.

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Ottawa, Canada

Justin L Fortier