Smsc Holdings Sarl

Analog Devices Global Unlimited Company

Justin L Fortier

Ralph Mason

Christopher Andrew Devries

Renyuan Li

Rachel Katumba

Peter H R Popplewell

William Kung

Multiplying delay locked loops (MDLLs) with compensation for realignment error are provided. In certain implementations, an MDLL includes a control circuit, a multiplexed oscillator, and an integrate and subtract circuit. The control circuit selectively injects a reference clock signal into the multiplexed oscillator, which operates with an injected period when the reference clock signal is injected and with a natural period when the reference clock signal is not injected. The integrate and subtract circuit receives an oscillator signal from the multiplexed oscillator, and tunes an oscillation frequency of the multiplexed oscillator based on a difference between an integration of the oscillator signal over the injected period and an integration of the oscillator signal over the natural period.

Multiplying delay locked loops with compensation for realignment error

An audio amplifier system may include an audio CODEC/output (AOP) path featuring analog class-D amplifiers, and using Natural Sampling Pulse Width Modulation (PWM) to convert an analog input into a series of Rail-to-Rail pulses. The audio signal may be encoded in the average value of the PWM pulse train and may be recovered from the PWM signal by analog low pass filtering. The Class-D amplifiers may be designed with a negative feedback loop/network to compare the output signal with the input signal and suppress non-idealities introduced by the Class-D switching stage. Furthermore, operation of the AOP may be designed according to a separate signal transfer function and a separate noise transfer function, and 2order noise shaping may be performed at low power, with an optimized filter included in the feedback loop to achieve the best noise reduction at low power. Operation of the amplifier feedback network may be similar to that of a continuous time, low-pass delta-sigma modulator, but with a PWM loop wrapped around the class-D power amplifier.

Low-power class D amplifier using multistate analog feedback loops

Various embodiments of a radio-frequency (RF) transmitter receiver circuit that utilizes an injection locked oscillator may allow for the introduction of a DC offset to correct the RF signal. The DC offset may be adjusted to eliminate (or minimize) even order harmonics to correct for RF effects. The DC offset correction may be performed around the injection locked oscillator to target even order terms.

Reducing spurs in injection-locked oscillators

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Carleton Place, Canada

Justin L Fortier