Quantum Corporation

Maxtor Corporation

Justin J Koller

Bruce Douglas Buch

Diana L Langer

Nick Horgan

Timothy Proch

Matt Ball

Ben Sembera

A decoder to correct errors in data includes a plurality of cells. Each cell generates a partial syndrome based on data blocks and one or more redundancy blocks. Each cell generates a partial error value based on a portion of an inverse of an error location matrix that identifies locations of any data blocks having errors. A summation logic connected to the plurality of cells generates an error value based on the partial error values generated by the plurality of cells.

Error correction decoder using cells with partial syndrome generation

A programmable write equalization circuit includes a first digital clock that is used as a reference to indicate data rate, a second digital clock used to indicate write equalization quantization, a look-up table used to store waveforms used in equalizing the input from the first digital clock domain to the second digital clock domain, a counter used to indicate the number of bits within the look-up table that are to be used for each translation, a polarity detector used to detect the current state of the input data, a non-return-to-zero (NRZ) filter used to indicate the placement of data transitions and non-transitions, and a software interface including programmable registers to control each one of the parameters within the equalization circuit.

Programmable write equalization circuit

A non-volatile storage subsystem comprises a media I/O controller, a media access channel, and movable storage media. A non-volatile disk storage subsystem bas a read channel coupling a disk controller to a disk head assembly. A read channel interfacing subsystem is provided as part of the storage subsystem, and the read channel interfacing subsystem interfaces a disk controller to the read channel. The read channel interfacing subsystem comprises a set of process units and a pipeline manager.

Data transfer scheme for efficiently moving data through a high latency media access channel

A method of data transfer in a data processing system having at least one source buffer and at least one destination buffer. The source buffer includes a plurality of data blocks, each data block having an address and being for storage of data including an identifier uniquely identifying that data block. The destination buffer includes a plurality of data blocks corresponding to the data blocks of the source buffer, each destination block having an address and being for storage of data. Each source block identifier is a function of a corresponding destination block address. Transferring data from the source buffer to the destination buffer includes: (a) obtaining the address of a data block in the destination buffer to transfer data into; (b) obtaining the address of a corresponding data block in the source buffer to transfer data from; and (c) checking the integrity of said addresses before data transfer, including: (i) retrieving the source block identifier in the source block via the source block address; (ii) generating an expected identifier value for the source block from the address of the destination block via said function relation between the source block identifier and the destination block address; (iii) comparing the expected identifier value with the retrieved identifier value; and (iv) if there is a mismatch, signaling an error condition representing corruption of one or more of the source block and the destination block addresses.

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Glendale, CO, United States of America

Justin J Koller