International Business Machines Corporation

Justin Ginn

Tony Emile Sawan

Ryan Bergsma

Brandon Lackey

Ricardo Escobar

Hardware acceleration using a self-programmable coprocessor architecture may include determining that an instruction cache comprises an accelerable instruction sequence; instead of executing the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction; and receiving, from the accelerator complex, a result of the complex instruction.

Hardware acceleration using a self-programmable coprocessor architecture

Managing network communications is provided. An indication that a network device has been added to a local network is received. In response to receiving the indication that the network device been added to the local network, metrics corresponding to the network device added to the local network are detected. A device fingerprint corresponding to the network device added to the local network is generated based on the detected metrics.

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Austin, TX, United States of America

Justin Ginn