Cirrus Logic Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Silicon Laboratories Inc.

Justin Dougherty

John L Melanson

Timothy Joseph Dupuis

Christian Larsen

Alexander Barr

Vishnu Shankar Srinivasan

David E Bockelman

Marc Laurent Tarabbia

Eric Kimball

Aaron J Brennan

Scott Warrick

Ramya Balasundaram

Martin Joseph Gabriel, Iii

Vu N Do

David H Griffin

Ying Ying

A dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) may include a MOSFET having a channel region, a drain, and a source, a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region.

Dual gate metal-oxide-semiconductor field-effect transistor

In accordance with embodiments of the present disclosure, a method for identifying a location of an integrated circuit that is sensitive to RTS noise may include applying localized heat to a scan area of the integrated circuit, observing any change in one or more electrical parameters of the integrated circuit in response to the localized heat being applied to the scan area indicative of sensitivity to RTS noise, and identifying the location sensitive to RTS noise responsive to observing change in one or more electrical parameters of the integrated circuit indicative of sensitivity to RTS noise in response to the localized heat being applied to the scan area.

Random telegraph signal identification and measurement

In an embodiment, a power amplifier (PA) includes a signal processing path including gain stages to receive a radio frequency (RF) signal and to output an amplified RF signal, sensors coupled to the signal processing path each to sense a characteristic of operation of the PA, and a microcontroller configured to execute instructions and to receive the operation characteristic(s) and to control one or more parameters of the signal processing path responsive this operation characteristic.

Power amplifier having an integrated microcontroller

A test socket () includes first () and second () test leads and a first electrically conductive member (). The first test lead is adapted to contact a first external inductor terminal of an integrated circuit (). The second test lead () is adapted to contact a second external inductor terminal of the integrated circuit (). The first electrically conductive member () extends between the first test lead () and the second test lead (), thereby forming an inductance loop between the first external inductor terminal and the second external inductor terminal.

Test socket with integral inductor and method of manufacturing using such a test socket

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Austin, TX, United States of America

Justin Dougherty