3com Corporation

3com Technologies

Justin A Drummond-Murray

David J Law

Daniel M O'Keeffe

Robin Parry

Paul J Moran

Christopher Byham

Nicholas Mark Stapleton

Christopher Alan Walker

Nigel Horspool

Lee C Harrison

Annette E Sohor

Pauric O'Callaghan

Paul Flood

Ruben Aszkenasy

Rob Parry

Malcolm G Brown

Richard Ja Strike

A packet-switched network system comprises a multiplicity of multi-port network units each of which has first and second ports and other ports and transmission links coupling the first and second ports of said unit in a closed ring. The first and second ports and transmission links support duplex transmission of Ethernet data packets. Each unit transmits from said first and second ports packets including selected information enabling on reception of a packet at any of the units a determination of a number of hops from unit to unit around said ring said packet has made. Each unit has a forwarding database and in response to the said selected information controls the transmission of said packets in two directions around said ring, and each unit causes discard of packets which have according to said selected information circumnavigated the ring.

Ethernet units adapted for loop configuration and method of operating same

An Ethernet data packet including a VLAN tag header and a VLAN identification field is modified. The modification is accomplished by inserting in place of the VLAN tag header a field of the same size including selected information. The VLAN identification may be retained. The inserted field may include a first field indicating the presence of the VLAN identification field and a second field of selected information, the second field being longer than the first field.

Modification of tag fields in Ethernet data packets

Apparatus for performing a cyclic redundancy code check on a binary digital signal consisting of a variable multiplicity (M) of data bytes comprises a buffer register for temporarily storing in succession segments each consisting of an integral number (N) of bytes. Each successive segment is loaded into a cyclic redundancy checker which produces a remainder after performing polynomial division of the digital signal. When the number of bytes of the digital signal in the last segment is less than the integral plurality (N) that last segment is padded with constant data. The signal is deemed valid if the remainder matches any of a plurality of predetermined remainders each corresponding to the operation of the checker on a valid digital signal padded with zero to (N&minus;1) bytes of the constant data

Fast frame error checker for multiple byte digital data frames

A multiport network device includes a multiplicity of receive queues, a multiplicity of transmit queues and a forwarding engine for transferring entries from the receive queues to the transmit queues. When a transmit queue is greater than a first hysteresis point, the forwarding engine prevents transfer of entries from a receive queue to the transmit queue and transfer of entries to the transmit queue is allowed when the length of the transmit queue falls below a second hysteresis point.

Network switch including hysteresis in signalling fullness of transmit queues

A network switch which can perform in respect of addressed data packets source address and destination address look-ups in a forwarding database includes a control which inhibits the performance of source address look-ups if the length of a respective receive queue of packets is greater than a threshold. The inhibition may endure until the length of the receive queue falls below a second threshold lower than the first. The inhibition may not be applied if the respective receive queue is subject to head of line blocking

Network switch including restriction of source address look-ups based on receive queue length

A network switch maintains transmit queues and for each transmit queue a table which identifies the contributions of traffic received at the ingress ports to that queue. When a queue is too long, a pause frame is dispatched from a selected one of the ingress ports. The ingress port may be selected as that making the greatest contribution to the transmit queue. However, a control algorithm allows ports carrying high priority traffic to be excluded from the selection.

Communication switch including input bandwidth throttling to reduce output congestion

A multi-port data communication device includes a common central memory through which all data packets must pass. Packet data is written to and read from the common memory space in bursts in response to receive write requests and transmit read requests. A transmit read request for a first burst of data in a packet has in a central arbiter a relatively low priority and transmit read requests for a second and any subsequent burst of data in a packet have in the central arbiter a relatively high priority. Preferably the receive write requests have in said central arbiter a priority intermediate said relatively low priority and said relatively high priority. The priority system reduces the likelihood of underrun and overrun particularly when the burst size is generally smaller than the packet size.

Inhibition of underrun in network switches and the like for packet-based communication systems

A packet memory system including a memory space having a multiplicity of addressable memory locations for the storage of data packets, pointer control means for generating a write pointer which progressively defines where data is to be written to the memory space and a read pointer which progressively defines where data is to be read from the memory space and an ageing clock which defines a succession of intervals. The pointer control means generates a 'current' pointer and a 'discard' pointer and for each interval is operative to cause the &lsquo;current&rsquo; pointer to correspond to an immediately previous value of the write pointer and to cause the discard pointer to correspond to an immediately previous value of the said current pointer. In this manner the portion of the memory space between the &lsquo;discard&rsquo; pointer and the read pointer denotes data which has been in said memory space for at least two of said intervals. The system thereby defines ageing by means of pointers and avoids the ambiguities or inconvenience of known recycling ageing schemes.

Ageing of data packets using queue pointers

A network in which a data packet is altered, for instance by the insertion or removal of a data portion such as a VLAN tag. The data of the data packet is read out of memory to an output means which forms the altered data packet with a new FCS portion and to a checking means which checks the integrity of the input packet using the existing FCS. The possibility for discrepancies to occur between the data supplied to the output and checking means is reduced.

Data packet transmission

A socket connector has a single socket including fiber optic terminals,and wire terminals,and is adapted to receive alternatively in respectively inverted positions either a first plug connector for cooperation with the fiber optic terminals or a second plug connector for cooperation with the wire terminals, in each case without engagement with the terminals with which the plug should not cooperate. The connector includes respective latching slots,and,in opposite walls,and,for the respective plug connectors.

Dual-mode socket connectors

A clock selector circuit for selecting a single output clock signal from a multiplicity of input clock signals, each constituted by transitions between binary states, comprises a multiplicity of D-bistables each having a clock input coupled to receive the respective one of the input clock signals, a D-input coupled to receive a hold signal common to the bistables, and an output for providing a respective hold signal. A first multiplexer has inputs coupled to receive the respective input clock signals and is operative to select in response to the selection signal one of said input signals. A second multiplexer has inputs coupled to receive the respective hold signals and is operative to select in response to the selection signal the hold signal corresponding to the clock signal selected by the first multiplexer. A gate is coupled to receive both the clock signal selected by the first multiplexer and the hold signal selected by the second multiplexer and asserts an output whichever of the input signals to the gate may be asserted. The assertion of the common hold signal precedes a chance in state of the selection signal and endures at least until all the hold signals have been asserted and a change in state of the selection signal has occurred. The circuit facilitates glitch-free clock multiplexing.

Glitch free clock multiplexer circuit

The occurrence of collision and activity in a computer network is indicated by activation of a visual indication device. The device is activated for periods which are longer than the actual periods of collision and activity to permit the human eye to register the visual indications. This is particularly useful for high speed networks where the periods of collision and activity may be very brief.

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Chorleywood, United Kingdom

Justin A Drummond-Murray