Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Process Computer Engineering, Inc.

Jushi Ide

Tadaaki Bandoh

Hidekazu Matsumoto

Seiichi Yasumoto

Yasushi Fukunaga

Yoshihiro Miyazaki

Hitoshi Fushimi

Ryosei Hiraoka

Tetsuya Kawakami

Hiroshi Kuwahara

Kotaro Hirasawa

Takeshi Kato

Shinichiro Yamaguchi

Sadao Mizokawa

Hiroaki Nakanishi

Masakazu Okada

Kazuyuki Kodama

Soichi Takaya

Yasuji Kamata

Shigeru Yabuuchi

Kenkichi Yamashita

Takayuki Morioka

Hirokazu Hirayama

Yukio Kawamoto

Hiroshi Watanabe

Masayuki Sakata

Yoshiaki Takahashi

Yoshiki Kobayashi

Koji Takahashi

Takuji Hamada

Hiroshi Kuwabara

Masahiro Takahashi

Atsuo Yoshida

Toshiro Kamiuchi

Takeshi Katoh

Takeyuki Endo

Atomi Noguchi

Ken Onuki

Takeyuki Endoh

Hisayuki Maruyama

Toshihiko Uchiyama

Shigeo Abe

Masato Satake

Toshio Ishihara

Koshirou Adachi

Yoshiji Ito

Hiroshi Kaita

Yasuo Hosoda

Hiroaki Ohnishi

Tadaaki Okada

Morioka Takayuki

A plurality of different fault locating functions are provided in a communication system comprising a plurality of terminals connected to a data transmission channel. The functions are at different levels, respectively, ranging from a level for rapid fault location to a level for reliable and sure fault location. Upon detection of an occurrence of a fault, one fault locating function is performed. If the fault is not located accurately located, another fault locating function of a level for more reliable is performed, thus the functions are performed sequentially in the order from the level for rapid location to the level for more deliberate and reliable location. Preferably, the channel is reconfigured to avoid the fault, according to the fault located by the functions of the respective levels. With this arrangement, a fault which does most possibly occur can be located quickly, while another fault difficult to locate can be located accurately.

Method of locating fault of communication system

Method and apparatus for instruction restart processing in a microprogram-controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

System for storing restart address of microprogram, determining the

Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

Suspended instruction restart processing system based on a checkpoint

A housing for accomodating an electronic apparatus including heat-generating parts, in which the surface of a cooling air inlet port in the front or rear side of the housing is formed in arcuate fashion and recessed as viewed from the interior of the housing. As a result, the velocity of air introduced is remarkably reduced thereby improving the heat radiation of the housing.

Housing for electronic apparatus

In a vector processor including pipeline processors and means for synchronously controlling each component, there is provided an FIFO memory for temporarily storing the output of each pipeline processor and for outputting the stored data, in the order of storing, to at least one of the pipeline processors. Since intermediate result of operation is temporarily stored in the FIFO memory, a simple microprogram can be used and thus the capacity of the memory for microprogram can be reduced even if the successive intermediate results for calculation of vector elements are overlapped within the loop of the microprogram.

Vector processor

A multicomputer system having dual common memories in which specified address areas are set within the common memories. The specified address areas are accessible irrespective of whether a CPU is in an online mode or a debug mode, while any area other than the specified address areas is accessible only when the function mode of the common memory is in agreement with the access mode of the CPU. In correspondence with each CPU, addresses to be used by the CPU are divided into a plurality of groups of addresses, and the access modes are set for the respective address groups.

Multicomputer system having dual common memories

A loop transmission system having a plurality of data processor connected through respective transmission station with a common loop transmission line is disclosed. This system has a concentrator connected with a plurality of transmission stations through respective loop transmission lines. The concentrator changes the order of connection said loop transmission lines thereby to change the order of connected of said transmission stations on said loop transmission lines.

Loop transmission system having plural stations connected in a variable

A CRT picture display apparatus of the raster scan type comprises a cathode ray tube for raster scanning, a horizontal deflection circuit for supplying a horizontal deflection current to a horizontal deflection coil of the CRT, a vertical deflection circuit for supplying a vertical deflection current to a vertical deflection coil of the CRT, and a display data generator for supplying data to be displayed to the CRT. The horizontal deflection circuit produces as the horizontal deflection current a triangular current having one period which is twice a horizontal scanning period, and the triangular current has a first portion which increases in response to a horizontal sync signal at a predetermined inclination and a second portion which decreases in response to the next horizontal sync signal at the predetermined inclination and continues until the further next horizontal sync signal, whereby the period for a scanning line to proceed from lefthand end to righthand end of a raster on a screen of the CRT is made substantially equal to the period for the next scanning line to proceed from righthand end to lefthand end, and data is displayed during both the periods.

CRT picture display apparatus

In a floating point digital differential analyzer, multiplication and division of constants are carried out by an adder which truncates a summation SDY.sub.i of l secondary increments calculated by ##EQU1## into a third increment having an n-bit mantissa including a sign bit, and an integrator for carrying out an integration of

Floating point digital differential analyzer

A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flat is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.

Central processing unit for executing instructions of variable length

In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.

Bus selection control in a data transmission apparatus for a

A data processing system for supporting a virtual memory is disclosed. Prior to the start of main memory write operation, a processor checks to see if a store buffer has a vacant area to store data to be written into a main memory to execute a current instruction. If a page fault occurs during the main memory write operation, the processor continues to store the subsequent write data for the current instruction and the corresponding virtual or logical addresses in the store buffer to complete execution of the current instruction.

Data processing system

In order to deliver an input signal of each operation cycle after a desired time delay, there are disposed data memory means for storing the input signal, counter means for appointing write addresses of the data memory means, and address memory means for appointing read addresses of the data memory means. The address memory means is divided into partial memory areas equal in number to time delay elements, whereupon while sampling the input signal at a predetermined sampling period and changing the count value of the counter means one by one for each of the desired time delay elements at each sampling point, the variations of the input signal in a sampling interval between the particular sampling point and the adjacent sampling point are successively written into the memory means. Further, while changing the contents of the partial memory areas corresponding to the desired time delay element to the number of the time delay elements in each sampling interval, the variations in a sampling interval preceding a predetermined sampling number to the particular sampling interval are successively read out from the memory means. The input signal of each operation cycle in the preceding sampling interval is presumed by an interpolation operation based on the variation and the sampling period, and the result is used as an output signal of the desired time delay element.

Method of generating time delay

A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to execute an instruction and includes a cache memory which is accessed with a virtual address. One of the plurality of processors is a file processor which accesses the main memory with a virtual address to transfer data between the main memory and an external memory. The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.

Shared virtual address translation unit for a multiprocessor system

A central station and a plurality of transmission stations are connected in cascade by a serial transmission line, and constitute a looped data highway system. The central station controls the whole system. The system allows the transmission station having a data signal transmission request to send out a data signal by means of a normal polling signal, but only the station having sent out the data signal by means of the preceding normal polling signal is allowed to send out the data signal again in response to a retry polling signal.

Data transmission system and method

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Mito, Japan

Jushi Ide