Nxp B.v.

Integrated Plasmonics Corporation

Jurriaan Schmitz

Franciscus Petrus Widdershoven

Erwin Hijzen

Raymond J E Hueting

Andreas Hubertus Montree

Michael A A In'T Zandt

Robert Joseph Walters

Albert Polman

Gerrit E J Koops

Claire Ravit

Ihor Brunets

Rita Victoire Theodosie Rooyackers

Michiel Slotboom

An integrated plasmonic sensing device is described wherein the integrated device comprises: at least one optical source comprising a first conductive layer and a second conductive layer, and a optical active layer between at least part of said first and second conductive layers; at least one nanocavity extending through said first and second conductive layers and said optical active layer, wherein said optical source is configured to generate surface plasmon modes suitable for optically activating one or more resonances in said nanocavity; and, at least one optical detector comprising at least one detection region formed in said substrate in the vicinity of said nanocavity resonator, wherein said optical detector is configured to sense optically activated resonances in said nanocavity.

Integrated plasmonic nanocavity sensing device

A vertical insulated gate transistor is manufactured by providing a trench () extending through a source layer () and a channel layer () towards a drain layer (). A spacer etch is used to form gate portions () along the trench side walls, a dielectric material () is filled into the trench between the sidewalls gate portions (), and a gate electrical connection layer () is formed at the top of the trench electrically connecting the gate portions () across the trench.

Vertical insulated gate transistor and manufacturing method

A method of manufacturing a semiconductor device comprising a silicon body () having a surface () provided with field isolation regions () enclosing active regions (). In this method, on the surface of the silicon body there is formed an auxiliary layer () of a material on which, during an oxidation treatment, a thicker layer of silicon oxide is formed than on the silicon of the silicon body. Here, an auxiliary layer comprising silicon and germanium is formed on the surface, said auxiliary layer preferably being a layer of SixGe1&#x2212;x&#x2212;yCy, where 0.70&#x3c;x&#x3c;0.95 and y&#x3c;0.05. Next, at the location of the field isolation regions to be formed, windows () are formed in the auxiliary layer and trenches () are formed in the silicon body. Next, on the walls () of the trenches, a silicon oxide layer () is provided and on the walls () of the windows a silicon oxide layer () is provided, both being formed by an oxidation treatment. The auxiliary layer is not oxidized throughout its thickness. After the oxidation treatment, a layer of insulating material () is deposited which fills the trenches and windows completely. Then, successively, a planarization treatment is carried out until the non-oxidized part of the auxiliary layer () is exposed, and the exposed part of the auxiliary layer is removed. Thus, field isolation regions () are formed having an edge () extending above the active regions ().

Method of manufacturing a semiconductor device with field isolation regions consisting of grooves filled with isolation material

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Hengelo, Netherlands

Jurriaan Schmitz