Koninklijke Philips Corporation N.v.

U.S. Philips Corporation

U.S. Phillips Corporation

Jurriaan Schmitz

Pierre Hermanus Woerlee

Andreas Hubertus Montree

Franciscus Petrus Widdershoven

Daniel Wilhelmus Elisabeth Verbugt

Edwin Roks

Michiel Slotboom

Youri V Ponomarev

A method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells (Mij) including a select transistor (T) with a select gate () and including a memory transistor (T) with a floating gate () and a control gate (). In a semiconductor body (), active semiconductor regions are formed which are mutually insulated by field oxide regions (). Next, the surface () is provided with a gate oxide layer () and a first layer of a conductive material wherein the select gate () is etched. Subsequently, the walls of the select gate extending perpendicularly to the surface are provided with an isolating material (). The gate oxide next to the select gate is replaced by a layer of tunnel oxide (). Next, a second layer of a conductive material (), an interlayer dielectric () and a third layer of a conductive material () are deposited. The control gate () extending above and next to the select gate is formed in the third layer. Using the control gate as a mask, the floating gate () is subsequently etched in the second layer of conductive material. In this method, the second layer is deposited in a larger thickness than the select gate, after which this layer is planarized prior to the deposition of the interlayer dielectric and the third layer of conductive material. In this manner, a compact memory cell can be manufactured.

Method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells

In a method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a transistor comprising a gate structure a patterned layer is applied defining the area of the gate structure Subsequently, a dielectric layer is applied in such a way, that the thickness of the dielectric layer next to the patterned layer is substantially equally large or larger than the height of the patterned layer which dielectric layer is removed over part of its thickness until the patterned layer is exposed. Then, the patterned layer is subjected to a material removing treatment, thereby forming a recess in the dielectric layer and a contact window is provided in the dielectric layer. A conductive layer is applied filling the recess and the contact window which conductive layer is subsequently shaped into the gate structure and a contact structure establishing an electrical contact with the surface of the semiconductor body

Method of manufacturing a semiconductor device

A detector and a camera system for electromagnetic radiation being integrated in a solid state substrate are disclosed. Said substrate comprises a first region of a first conductivity and a second region of a second conductivity, said first region being adjacent to said second region, and said first and second region forming a detection junction, at least part of said junction being substantially orthogonal with respect to the plane of the surface of the substrate above said detection junction. The camera system comprises a configuration of pixels in an imaging sensor being integrated in a solid state substrate, essentially each of the pixels comprising a region of a first conductivity type being at least partly surrounded by a region of a second conductivity type, thereby forming a junction region, and wherein the region of the first conductivity type includes at least one contact area. The camera system further comprises means for collecting charge carriers being generated by the radiation impinging on said substrate at least in said region of said first conductivity type and in said junction region, in said contact area.

Solid state imaging sensor in a submicron technology and method of manufacturing and use of a solid state imaging sensor

In transistors with sub-micron channels, short-channel effects, such as a lowering of the threshold voltage, are usually suppressed by means of a halo (or pocket) implant in the source/drain regions, which operation is performed jointly with the LDD implantation. The halo implant, however, decreases the analog performance of transistors. To combine suppression of short-channel effects with a high analog performance, it is proposed to provide only transistors T , which are not intended for analog functions with the halo implant ( ), and to mask the analog transistors T with a mask ( ) against the halo implant. To avoid short-channel effects in T , this transistor is provided with a channel whose length is larger than that of transistor T .

Integrated circuit

A semiconductor device comprising a non-volatile memory cell, for storing at least one bit, in a semiconductor substrate ( ) having, in the substrate, a source region ( ), a drain region ( ) and a channel region ( ) between the source ( ) and drain ( ) regions, and having, on top of the substrate, a floating gate ( ) separated from the channel region ( ) by a floating gate insulating layer, a select gate ( ) adjacent to the floating gate and separated from the channel region by a select gate insulating layer ( ), and a control gate ( ) separated from the floating gate ( ) by a control gate insulating layer, the floating gate being a non-conducting charge trapping dielectric layer ( ).

Semiconductor device

In a method of manufacturing a semiconductor device comprising a transistor having a gate insulated from a channel region at a surface of a semiconductor body by a gate dielectric, an active region of a first conductivity type is defined at the surface of the semiconductor body , and a patterned layer is applied consisting of refractory material, which patterned layer defines the area of the planned gate to be provided at a later stage of the process and acts as a mask during the formation of a source zone and a drain zone of a second conductivity type in the semiconductor body In a next step, a dielectric layer is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess in the dielectric layer at the area of the planned gate. Then, impurities are introduced via the recess into the channel region of the semiconductor body in a self-registered way by using the dielectric layer , as a mask and an insulating layer is applied, forming the gate dielectric, on which insulating layer a conductive layer is applied thereby filling the recess, which conductive layer is shaped into the gate of the transistor.

In a method of manufacturing a semiconductor device comprising a non-volatile memory element, an active region of a first conductivity type is defined at a surface of a semiconductor body , and a patterned layer is applied, which patterned layer acts as a mask during the formation of a source zone and a drain zone of a second conductivity type in the semiconductor body . Then, a dielectric layer is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess in the dielectric layer . In this recess a first insulating layer is applied providing a floating gate dielectric , to which first insulating layer a first conductive layer is applied filling the recess in the dielectric layer , which first conductive layer is shaped into a floating gate by means of masked etching. The floating gate has a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body and sidewall portions extending substantially perpendicularly to the surface of the semiconductor body . In a next step, the floating gate is covered with a second insulating layer providing an inter-gate dielectric , to which second insulating layer a second conductive layer is applied, which is shaped into an overlapping control gate . The control gate is capacitively coupled to the substantially flat surface portion of the floating gate and to at least the sidewall portions of the floating gate situated adjacent to the source zone and the drain zone of the memory element.

The invention relates to a method of manufacturing a (horizontal) MOST, as used, for example, in (BI)CMOS ICs. On either side of a gate electrode (,), the surface of a silicon substrate (,) which is positioned above a gate oxide (IA) is provided with a dielectric layer (,B) at the location where a source (,) and drain (,) are to be formed, which dielectric layer includes a thermal oxide layer (,B) to be formed as the starting layer. The source (,) and/or drain (,) is/are provided with LDD regions (,A,,A) and the remaining parts (,B,,B) of the source (,) and drain (,) are provided by an ion implantation (I,) of doping atoms into the silicon substrate (,). A MOST obtained in this way still suffers from so-called short-channel effects, resulting in a substantial dependence of the threshold voltage upon the length of the gate electrode (,), in particular in the case of very short lengths of the gate electrode (,). In a method according to the invention, the LDD regions (,A,,A) are made as follows: in a first step, suitable doping atoms (D) are implanted into the dielectric layer (,B), in a second ion implantation (I,), and subsequently in a second step, a part of the doping atoms (D) is diffused from the dielectric layer (,B) into the silicon substrate (,), whereby the LDD regions (,A,,A) are formed. This method enables a MOST with excellent properties to be obtained, for example with a flatter profile of the threshold voltage versus the gate-electrode (,) length (curve,) than in conventionally made MOSTs (curve,). This result is obtained in a simple and reproducible manner.

Method of manufacturing a semiconductor device comprising a MOS transistor

To obtain a high mobility and a suitable threshold voltage in MOS transistors with channel dimensions in the deep sub-micron range, it is desirable to bury a strongly doped layer (or ground plane) in the channel region below a weakly doped intrinsic surface region, a few tens of nm below the surface. It was found, however, that degradation of the mobility can occur particularly in n-channel transistors owing to diffusion of boron atoms from the strongly doped layer to the surface, for example during the formation of the gate oxide. To prevent this degradation, a thin layer,of Si,Ge,inhibiting boron diffusion is provided between the strongly doped layer,and the intrinsic surface region,, for example with x&equals;0.3. The SiGe layer and the intrinsic surface region may be provided epitaxially, the thickness of the SiGe layer being so small that the lattice constants in the epitaxial layers do not or substantially not differ from those in the substrate,in a plane parallel to the surface, while a sufficient diffusion-inhibiting effect is retained. Since SiGe has a diffusion-accelerating rather than decelerating effect on n-type dopants, the ground plane of a p-channel transistor in a CMOS embodiment is doped with As or Sb because of the low diffusion rate of these elements in pure silicon.

Si-Ge CMOS semiconductor device

A method of manufacturing a semiconductor device with a MOS transistor having an LDD structure. A gate dielectric (,) and a gate electrode (,) are formed on a surface (,) of a silicon substrate (,). The surface adjacent the gate electrode is then exposed, and a layer of semiconductor material (,) is formed on an edge (,) of the surface adjoining the gate electrode. Ions (,) are subsequently implated, with the gate electrode and the layer of semiconductor material acting as a mask. Finally, a heat treatment is carried out whereby a source zone (,) and a drain zone (,) are formed through activation of the implanted ions and through diffusion of atoms of a dopant from the layer of semiconductor material. The portions (b) of these zones formed by diffusion are weakly doped here and lie between the more strongly doped portions (a) formed through activation of implanted ions and the channel zone (,). An LDD structure has thus been formed. In the method, a layer of semiconductor material formed by Si,Ge,, 0.1<x<0.6, is provided on the edge adjoining the gate electrode. This layer is etched away selectively after the heat treatment. The formation of parasitic drain-gate capacitances is counteracted thereby.

Manufacture of a semiconductor device with a MOS transistor having an LDD structure using SiGe spacers

In a method of manufacturing a semiconductor device comprising a field-effect transistor and a non-volatile memory element at a surface of a semiconductor body, a first and a second active region of a first conductivity type are defined at the surface of the semiconductor body for the transistor and the memory element, respectively. The surface of the semiconductor body is subsequently coated with a first insulating layer providing a sacrificial gate dielectric of the transistor and a floating gate dielectric of the memory element, which first insulating layer is then covered by a silicon-containing layer providing a sacrificial gate of the transistor and a floating gate of the memory element. After formation of the sacrificial gate and the floating gate, the transistor and the memory element are provided with source and drain zones of a second conductivity type. In a next step, a dielectric layer is applied, which is removed over at least part of its thickness by means of a material removing treatment until the silicon-containing layer at the first and the second active region and is exposed, after which the silicon-containing first active region are removed, thereby forming a recess in the dielectric layer. Subsequently, a second insulating layer is applied at the second active region providing an inter-gate dielectric of the memory element, and a third insulating layer is applied at the first active region providing a gate dielectric of the transistor. After formation of the gate dielectric and the inter-gate dielectric, a conductive layer is applied which is shaped into a gate of the transistor at the first active region and a control gate of the memory element at the second active region.

Method of manufacturing a nonvolatile memory

In the known replacement gate process, the relatively high-ohmic poly gate is replaced by a low-ohmic metal gate by depositing a thick oxide layer and subsequently planarizing this layer by CMP until the gate is reached, which gate can be selectively removed and replaced by a metal gate. The process is simplified considerably by providing the gate structure as a stack of a dummy poly gate (,) and a nitride layer (,) on top of the poly gate. When, during the CMP, the nitride layer is reached, the CMP is stopped, thereby precluding an attack on the poly. The nitride and the poly are selectively removed relative to the oxide layer (,).

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Eindhoven, Netherlands

Jurriaan Schmitz