Sun Microsystems, Inc.

Oracle International Corporation

Apple Inc.

Other

Jurgen M Schulz

Brian L Smith

Rohit Kumar Gupta

Rohit Natarajan

Vishak Chandrasekhar

Srinivasa Rangan Sridharan

Jyh-Ming Jong

Christopher D Shuler

Thomas T Zou

Drew George Doblar

Harshavardhan Kaushikkar

Paul N Loewenstein

Thomas M Wicki

Anders Landin

Andrew E Phelps

Chung-Hsiao Wu

Michael J Grubisich

Wayne F Seltzer

Brian McGee

Bharat K Daga

Tai Quan

Connie W Cheung

Richard S Knight

Debaleena Das

Kenneth Chiu

Lee A Warner

Yu-Cheng Chiu

Yu-cheng Chiu

Sridhar Vakada

David C Stratman

Daniel F McMahon

Rajnikanth Joshi

Tin Y Lam

A non-transitory computer-readable medium is disclosed, the medium having instructions stored thereon that are executable by a computer system to perform operations that may include allocating a plurality of storage locations in a system memory of the computer system to a buffer. The operations may further include selecting a particular order for allocating the plurality of storage locations into a cache memory circuit. This particular order may increase a uniformity of cache miss rates in comparison to a linear order. The operations may also include caching subsets of the plurality of storage locations of the buffer using the particular order.

Allocation of a buffer located in system memory into a cache memory

A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.

Configurable interface circuit

An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

Dynamic allocation of cache memory as RAM

A winged visor stiffener for a hat's bill. A flat horizontal front section is connected to two angled offset sections. Two flat horizontal wings are connected to the two angled offset sections. The winged visor stiffener is sewn into the hat's bill via a plurality of rows of tight stitching. The winged visor stiffener provides protection to the wearer's face from the sun while optimizing peripheral vision and prevents the bill from flopping up or down in wet and windy conditions.

Winged visor stiffener for hat's brim

A directory structure that may allow concurrent processing of write-back and clean victimization requests is disclosed. The directory structure may include a memory configured to store a plurality of entries, where each entry may include information indicative of a status of a respective entry in a cache memory. Update requests for the entries in the memory may be received and stored. A subset of previously stored update requests may be selected. Each update request of the subset of the previously stored update requests may then be processed concurrently.

Reducing cache coherence directory bandwidth by aggregating victimization requests

Integrated circuit devices, methods, and other embodiments associated with power throttling with temperature sensing and activity feedback are described. In one embodiment, an integrated circuit device includes temperature sensing logic, activity sensing logic, comparison logic, and signal logic. The temperature sensing logic is configured to output a temperature signal indicative of a temperature of a selected region of the device. The activity sensing logic is configured to output an activity signal indicative of a level of activity of a selected device function. The mode selection logic is configured to select the temperature signal or the activity signal. The comparison logic is configured to compare the selected signal to a series of threshold levels and output a comparison result. The signal logic is configured to generate a throttle signal based on the comparison result. The throttle signal is used to control a frequency of operation of a selected device component.

Power throttle mechanism with temperature sensing and activity feedback

A system, comprising: a first local controller (LC) having a first position in a ring network and comprising a first LC cycle counter; a second LC having a second position in the ring network and comprising a second LC cycle counter; and a central controller (CC) connected to the ring network and comprising: a data structure linking the first LC to the first position and linking the second LC to the second position; and a CC cycle counter.

Transfer of information within an ASIC using a slotted ring based protocol

The disclosed embodiments disclose techniques for performing physical domain error isolation and recovery in a multi-domain system, where the multi-domain system includes two or more processor chips and one or more switch chips that provide connectivity and cache-coherency support for the processor chips, and the processor chips are divided into two or more distinct domains. During operation, one of the switch chips determines a fault in the multi-domain system. The switch chip determines an originating domain that is associated with the fault, and then signals the fault and an identifier for the originating domain to its internal units, some of which perform clearing operations that clear out all traffic for the originating domain without affecting the other domains of the multi-domain system.

Physical domain error isolation and recovery in a multi-domain system

Systems, methods, and apparatus for generating data packets and testing a packet switching system are provided. For example, a data packet diagnostic system includes an input queuing subsystem comprising a set of data queues, an injecting unit, and a diagnostic unit. Each data queue is coupled with a separate functional read/write path and debug read/write path. The injecting unit injects test data packets into at least one of the data queues via its respective debug read/write path. The test packets can then be processed (e.g., routed) through a data packet processing environment. In some implementations, packets are communicated via the data packet processing environment back to the input queuing subsystem, where the diagnostic unit can read present contents of at least one of the data queues to determine whether the present contents satisfy a predetermined test profile according to the injected data packets.

Integrated test packet generation and diagnostics

A multiple clock domain system. A system comprises two clock domains which receive a source clock signal. The first domain includes a first clock signal with a first frequency and the second domain includes a second clock signal with a second frequency. A ratio of the first frequency to the second frequency is N:M. The first domain is configured to initialize a count to N, if N is less than 2*M; and initialize the count to M, if N is not less than 2*M. Subsequently, on each cycle of the first clock signal, the first domain adds (M-N) to the count and asserts a sample enable signal, if the count is greater than or equal to N; and adds a value equal to M to the count and negates the sample enable signal, if the count is not greater than or equal to N.

Generating a clock crossing signal based on clock ratios

A memory system comprising router nodes. A plurality of router nodes are configured to route data between a memory controller and memory modules. The topology of the system comprises a hierarchy of one or more levels. Each of the levels includes one or more router nodes which may be configured to forward received data to another router node at the same level, or forward received data to a next lower level in the hierarchy. Router nodes in the system are configured to correspond to a particular level and position within the hierarchy. The memory controller generates a broadcast transaction to router nodes in the system. In response to receiving the transaction, the router nodes configure their internal routing mechanisms. Subsequently, the controller generates a memory access which is then routed by the router nodes to the target memory modules. Routing is such that memory modules not targeted by the memory access do not see the memory access.

Memory system topology

A device configured to recover and repeat source synchronous data. In one embodiment, the device is configured to receive source synchronous data via a first interface, recover the received data utilizing a corresponding received source synchronous clock signal, and transmit the recovered data and a corresponding clock signal in a source synchronous manner. In one embodiment, the device is configured to operate as a repeater without benefit of an internal clock signal. In addition, the device may be configured to remove data jitter and renew or restore amplitude to attenuated signals prior to retransmission.

Source synchronous bus repeater

A computer system including a memory controller configured to perform pre-fetch operations. A computer system includes a first system memory, a second system memory and a first and a second memory controller which are coupled to the first and second system memories, respectively. Each system memory may include at least one memory module including volatile storage. The first memory controller may be configured read data from the first system memory corresponding to an address of a current memory request. Further the second memory controller may be configured to selectively pre-fetch data from the second system memory depending upon selected address bits of the address of the current memory request.

Computer system including a memory controller configured to perform pre-fetch operations

A method and mechanism for testing communication links. A transmitter contact, or transmission point, is assigned a unique identifier. During a given test, the transmitter conveys a test pattern to a receiver via a link. Following this test pattern, the transmitter transmits a bit of its unique identifier to the receiver. The receiver receives both the test pattern and the identifier bit, and determines whether the received test pattern matches an expected value. If the test pattern was correctly received by the receiver, the receiver transmits the received identifier bit back to the transmitter. However, if the received test pattern is not correct, the receiver complements the received identifier bit and transmits the complemented bit back to the transmitter. The transmitter receives the identifier bit from the receiver and determines whether it matches the identifier bit which was originally transmitted by the transmitter. If the returned identifier bit does not match what was originally transmitted, the transmitter records an error.

Ibist identification loopback scheme

A system and method for the static scheduling of test cases. A static scheduler is used to schedule the entire verification test of an integrated circuit in advance. The static scheduler is used in conjunction with a hardware description language (HDL) circuit design, a virtual test bench, and simulation software. The static scheduler is configured to assign test events to resources, or functional units, of the integrated circuit design. Events for a resource are assigned to available time slots, or cycles. During event scheduling, the static scheduler is configured to ensure that there are no resource conflicts for a given time slot. By scheduling all test events in advance, pitfalls associated with dynamic scheduling may be avoided, such as those associated with the use of semaphores. By avoiding the use of semaphores, complex test scenarios and boundary conditions may be more fully exercised, as resources will not be locked. This may allow a more thorough verification of an integrated circuit design.

Growing community of inventors

Pleasanton, CA, United States of America

Jurgen M Schulz