Infineon Technologies Ag

Siemens Aktiengesellschaft

Jürgen Lindolf

Thoai-Thai Le

Andreas Felber

Martin Brox

Helmut Schneider

Michael Bernhard Sommer

Helmut Fischer

Florian Schamberger

Till Schlösser

Valentin Rosskopf

Eckhard Brass

Ulrich Frey

Bernhard Kowalski

Sibina Sukman

An integrated circuit with electrostatic discharge protection includes a first transistor with a source terminal, a drain terminal and a gate terminal, and a second transistor with a source terminal, a drain terminal and a gate terminal. The gate terminal for each of the first and second transistors is connected to the drain terminal. The first transistor is connected in series with the second transistor by one of the drain and source terminals of the first transistor being connected to one of the drain and source terminals of the second transistor. The series circuit formed by the transistors is connected to an input terminal of the integrated circuit or to a supply terminal and a terminal that applies the reference potential of the integrated circuit. The series circuit of the transistors is dimensioned by the number of transistors and the setting of the channel length and channel width ratios of the transistors.

Integrated circuit with electrostatic discharge protection

The invention relates to a semiconductor circuit () having an electrically programmable switching element (), an 'antifuse', which includes a substrate electrode (), produced in a substrate () which can be electrically biased with a substrate potential (Vo), and an opposing electrode () which is isolated from the substrate electrode () by an insulating layer (), where the substrate electrode () includes at least one highly doped substrate region (), and where the opposing electrode () can be connected to an external first electrical potential (V+) which can be provided outside of the semiconductor circuit (). In line with the invention, the substrate electrode () can be connected to a second electrical potential (V&#x2212;), which is provided inside the circuit and which, together with the external first potential (V+), produces a higher programming voltage (V) than the external first potential (V&#x2212;) together with the substrate potential (Vo). In addition, the substrate electrode () is shielded from the substrate potential (Vo) by a current barrier layer (). This allows the second potential to be lowered below the substrate potential or to be raised above it; the resulting increased programming voltage does not endanger other circuit regions.

Integrated semiconductor circuit with an electrically programmable switching element

Method for producing an antifuse in a substrate, a first interconnect being applied to the substrate, a dielectric layer being applied at an end face of the first interconnect, which end face essentially runs vertically with respect to the substrate, a second interconnect being applied in such a way that it adjoins the dielectric layer with an end face, with the result that an antifuse structure is formed.

Method for producing an antifuse in a substrate and an antifuse structure for integration in a substrate

A method for determining resistances at a plurality of interconnected resistors in an integrated circuit and a resistor configuration in which the resistors are interconnected to form a ring structure. Two measurement pads are in each case provided at the nodes between two resistors. The measurement pads can be used for feeding in current and for measuring voltage according to the known four-point measurement method. The effect of the ring structure is that fewer measurement pads are required, in contrast to the customary series circuit of resistors. By way of example, in the case of a ring structure with four resistors, two measurement pads are advantageously saved. The consequently reduced chip area required for the ring structure is advantageous particularly in the case of test circuits, which can be arranged for example in the narrow sawing frame between two chips.

Method and test structure for determining resistances at a plurality of interconnected resistors in an integrated circuit

A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of the transistors are located on both sides of active webs running parallel to one another and are connected to a superimposed metal plane by word line or CS contacts. To insulate these word line contacts from the other elements of the transistor array and of the cell array, the word line contacts are located in deep trenches that are introduced into the webs.

Transistor array and semiconductor memory configuration fabricated with the transistor array

An integrated memory has memory cells disposed in a cell array at crossover points of bit lines and word lines for storing information items. In addition, the memory has a word line decoder by which the word lines can be addressed, and at least one evaluation unit for evaluating the information items read from the memory cells onto the bit lines and the evaluation unit has an activation input. In addition, the integrated memory has a logic unit for performing an OR function and has inputs connected to that end of each of the word lines which is remote from the word line decoder. The logic unit further has an output connected to the activation input of the evaluation unit. The logic unit serves for time-optimized activation of the evaluation unit as soon as one of the word lines has been selected by the word line decoder.

Integrated circuit memory having a sense amplifier activated based on word line potentials

In an integrated semiconductor memory having a memory cell array divided into memory banks, supply potentials with high drive capability are applied to the memory banks only if the respective memory bank is activated for access to a memory cell. For this purpose a supply voltage assigned to the respective memory bank is controlled by the same address signal as the memory bank. The supply voltage sources generate a word line potential, a bit line potential or a substrate potential. As a result, a power loss is reduced.

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Friedberg, Germany

Jürgen Lindolf