U.S. Philips Corporation

Jurgen Lenth

Gerhard Pletz-Kirsch

Walter H Demmer

Rolf D Gutsmann

A synchronizing arrangement for a picture display device includes a synchronizing signal separating stage in which horizontal synchronizing pulses are recovered from a television signal applied to the synchronizing arrangement. In addition, the synchronizing arrangement includes a horizontal synchronizing circuit, more specifically a phase-locked loop, to which the horizontal synchronizing pulses are applied for the purpose of synchronization. When, switching criterion is present for a first presettable number of picture lines, the horizontal synchronizing circuit is switched to a fixed rated frequency. When the switching criterion is not satisfied anymore, the horizontal synchronizing circuit is switched back to synchronization by the horizontal synchronizing pulses after a second presettable number of picture lines.

Synchronizing arrangement for a picture display device

A digital synchronizing arrangement for a picture display device includes a synchronizing signal separator stage in which horizontal sync pulses are derived from a digital television signal applied to the synchronizing arrangement and which includes a horizontal synchronizing signal. A phase-locked loop receives the horizontal sync pulses for its synchronization. For the purpose of suppressing signal disturbances, a pulse of a first switching signal derived from the phase-locked loop is generated each time at the expected instants of the horizontal sync pulses. Furthermore, a pulse of a second switching signal is generated each time in a predetermined time interval after each pulse of the first switching signal. The first horizontal sync pulse which occurs during a pulse of the first switching signal is applied to the phase-locked loop, whereas horizontal sync pulses subsequently occurring in the interval until the next pulse of the second switching signal are not applied to the phase-locked loop. All horizontal sync pulses subsequently occurring until the next pulse of the first switching signal are applied to the phase-locked loop if no horizontal sync pulse appeared during the pulse of the first switching signal.

Digital synchronizing circuit insensitive to noise in a TV signal

A digital phase-locked loop comprises a phase comparator, a controllable oscillator whose output signal is compared with an input signal in the phase comparator, and a loop filter preceding the oscillator. The filter comprises a clocked input register for storing the last phase-measuring value of the phase comparator, and an integrator which comprises a clocked register whose output signal is fed back to the register input. When the input signal of the phase comparator is absent or disturbed, a switching signal is generated which immediately erases the input register in the loop filter and after whose appearance the register in the integrator of the loop filter is reset to zero within a limited number of clock cycles.

Digital phase-locked loop

A frequency-modulated input signal is converted at an adequately high sampling rate into a time-discrete and amplitude-discrete digital signal. This digital signal is applied to a simple transversal filter, having a sloping amplitude characteristic, more specifically having a sin.sup.2 transfer function and a constant group delay time, and to a delay device having a time delay which is equal to the group delay time. The output signal of the filter is applied to a numerator input of a divider (6) and the output signal of the delay device to a denominator input the divider (6) whose quotient contains the frequency corresponding to the amplitude characteristic of the filter. In this manner, a frequency demodulator having a very good AM-suppression and an adequate linearity at broad-band-FM is realized. The divider is formed, in accordance with the 'pipeline principle', from a plurality of identically constructed sections corresponding to the number of bit positions of the processed digital signals. As a result thereof a sufficiently high processing speed can be accomplished with very little cost. A correction circuit is provided to avoid faults and inaccuracies, respectively, in the case of small denominators.

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Hamburg, Germany

Jurgen Lenth