Infineon Technologies Ag

Globalfoundries Inc.

Siemens Aktiengesellschaft

Qimonda Ag

Infineon Technologies Dresden Gmbh & Co . Kg

Jürgen Faul

Thomas Schuster

Johann Alsmeier

Ulrich G Hensel

Jürgen Amon

Thomas Ruder

Thorsten E Kammler

Ulrike Gruening

Matthias Goldbach

Frank Jakubowski

Dirk Offenberg

Achim Gratz

Stefan G Block

Albrecht Kieslich

Frank Prein

Rudolf Strasser

Michael Zier

Arif A Siddiqi

Ingolf Lorenz

Giuseppe Curello

Swapnil Pandey

Ralf Müller

Haritez Narisetty

Wilfried H{umlaut Over (a)}nsch

A lateral high-voltage transistor includes a semiconductor substrate, a body region formed by dopant implantation in the semiconductor substrate, the body region having a lateral boundary, a dielectric layer arranged over the semiconductor substrate, and a structured gate layer arranged over the dielectric layer. The structured gate layer overlaps the body region in the semiconductor substrate in a zone between the lateral boundary of the body region and a gate edge of the structured gate layer. The lateral boundary of the body region is a boundary defined by dopant implantation.

Lateral transistor with self-aligned body implant

Embodiments of the present disclosure provide a circuit structure including: a first tap node, a first operational element coupled to the first tap node, the first operational element including at least one transistor having a back-gate, a second tap node coupled to the first operational unit, a second operational element coupled to the second tap node, the second operational element including at least one transistor having a back-gate, and a first back-gate biasing voltage regulator coupled to the second operational element and the first tap node. The first back-gate biasing voltage regulator is configured to supply the at least one transistor of the second operational element with a back-gate biasing voltage level that is different than a voltage level available to the second operational element from the second tap node.

Back-gate biasing voltage divider topology circuit structure

In fully depleted SOI transistors, specifically designed semiconductor materials may be provided for different types of transistors, thereby, for instance, enabling a reduction of hot carrier injection in transistors that are required to be operated at a moderately high operating voltage. To this end, well-controllable epitaxial growth techniques may be applied selectively for one type of transistor, while not unduly affecting the adjustment of material characteristics of a different type of transistor.

Process for forming semiconductor layers of different thickness in FDSOI technologies

It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.

Reducing antenna effects in SOI devices

A semiconductor structure having a plurality of gate stacks on a semiconductor substrate provided with a gate dielectric. The gate stacks have a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, and an upper third layer made of an insulating material, and a sidewall oxide on the sidewalls of the first and second layers. The sidewall oxide is thinned or removed on one of the sidewalls, and the gate stacks have sidewall spacers made of the insulating material.

Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure

A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

Method for fabricating a semiconductor structure

Method for the production of a semiconductor structure comprising a plurality of gate stacks on a semiconductor substrate which serve as control electrodes for a respective selection transistor of a corresponding memory cell comprising a storage capacitor. Gate stacks are provided next to one another on the substrate provided with a gate dielectric wherein the gate stacks have a lower first layer made of polysilicon, an overlying second layer made of metal silicide, and an upper layer made of silicon nitride. A sidewall oxide is formed on uncovered sidewalls of the first and second layers of the gate stacks, and at least partly the sidewall oxide is removed on those sidewalls of the gate stacks serving as a control electrode which are remote from the associated storage capacitor. Silicon nitride sidewall spacers are then formed on the gate stacks.

A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process uses individual process steps that are already used in the mass production of integrated circuits and accordingly can be configured for a high throughput.

Process for producing a doped semiconductor substrate

The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS, GS, GS, GS) on a semiconductor substrate (), having the following steps: application of the gate stacks (GS, GS, GS, GS) to a gate dielectric () above the semiconductor substrate (); formation of a sidewall oxide () on sidewalls of the gate stacks (GS, GS, GS, GS); application and patterning of a mask () on the semiconductor structure; and implantation of a contact doping () in a self-aligned manner with respect to the sidewall oxide () of the gate stacks (GS, GS) in regions not covered by the mask ().

A p-channel field-effect transistor is formed on a semiconductor substrate. The transistor has an n-doped gate electrode, a buried channel, a p-doped source and a p-doped drain. The transistor is fabricated by a procedure in which, after an implantation for defining an n-type well, an oxidation is performed to form a gate-oxide layer and n-doped polysilicon is subsequently deposited. The latter is doped with boron or boron fluoride particles either in situ or by a dedicated implantation step. In a thermal process, the boron acceptors penetrate through the oxide layer into the substrate of the n-type well, where they form a p-doped zone, which serves for counter doping and sets the threshold voltage. This results in a steep profile that permits a shallow buried channel. The control of the number particles penetrating through the oxide layer is achieved by nitriding the oxide layer in an NO atmosphere.

Method for fabricating a p-channel field-effect transistor on a semiconductor substrate

Improved techniques for quantifying proximity effects during fabrication of integrated circuits are disclosed. The improved techniques use active features formed on a semiconductor wafer to quantify proximity effects. According to the improved techniques, a device performance quantity for an active feature is measured, and then a feature length for the active feature is determined in accordance with the measured device performance quantity. The fabrication processing can then be evaluated and/or compensated based on the determined feature length. In one example, the active feature can be a metal-oxide semiconductor (MOS) transistor and the device performance quantity can be current.

Growing community of inventors

Radebeul, Germany

Jürgen Faul