Seiko Epson Corporation

Juraj Bystricky

Doug McFadyen

Lawrence P Chee

Brett Anthony Cheng

Tatiana Pavlovna Kadantseva

Keith Kejser

David M Tucker

Kevin Gillett

A system and method for facilitating software profiling procedures in a target device includes a target CPU that executes software instructions from target routines of the target device to perform various processing tasks. A program counter of the target device is periodically updated with a current program counter value corresponding to one of the software instructions that is being currently executed by the target CPU. A shadow register is advantageously implemented in the target device to be directly accessible by profiler software on a host computer. The shadow register is periodically updated with a profiling program counter value that corresponds to the current program counter value. The profiler software may then directly and transparently access the shadow register to read the profiling program counter value for performing the software profiling procedures.

System and method for facilitating software profiling procedures

A system and method for supporting variable-width memory accesses includes storage registers configured to store transfer data. The storage registers have a pre-determined storage register width. A host interface moves the transfer data to and from the storage registers. The host interface has a data transfer width that is greater than the storage register width. A memory access module analyzes a mode flag that is incorporated into a transfer address. The memory access module performs the memory access operation in a full mode if the mode flag is set to a full access state. Conversely, the memory access module performs the memory access operation in a partial access mode if the mode flag is set to a partial access state. In the partial transfer mode, the transfer data has a data width that is equal to the storage register width. The memory storage module is able to directly access a single one of the storage registers.

System and method for supporting variable-width memory accesses

A system and method for performing an interface save/restore procedure in an electronic device includes a processor that begins to execute a first task in conjunction with a host interface of a display processor. The processor subsequently receives an interrupt request for executing a second task that has a higher priority than the first task. A save/restore module responsively stores task states from the host interface into an interface states register. The task states correspond to an interrupted execution point in the first task. The processor temporarily stops the first task to execute the second task. The save/restore module restores the stored task states to the host interface after the second task is completed, and the processor may then efficiently resume the first task.

Saving/restoring task state data from/to device controller host interface upon command from host processor to handle task interruptions

A method for debugging including the steps of receiving code having a software breakpoint function therein, running the code for the purpose of debugging, monitoring the code to detect the presence of the software breakpoint function, recognizing the software breakpoint function, determining an action to be performed based on the software breakpoint function, and implementing the action. The present invention also includes an apparatus for implementing the method for debugging and a medium embodying a program of instructions for execution by a device to perform the method for debugging.

Software breakpoints implementation via specially named function

A computer system includes an operator input device, a central processing unit (CPU), and a display device, such as a liquid crystal display (LCD) or cathode ray tube (CRT) providing a visible image to the computer user as an output of computer activity. The computer system includes a video display controller (VDC) with a graphics generator. This VDC receives image information, such as text or graphics generated by the CPU, or retrieved by the CPU from another facility (such as a CD-ROM) of the computer system, and responsively provides image signals driving the CRT or LCD display. The VDC includes a power saving controller implementing one of several available power saving modes dependent upon one or more of several possible inputs. Each of the power saving modes includes the same list of VDC functions which may individually be enabled or disabled in each power saving mode dependent upon a bit value entered into a register of the power saving controller. Each of the power saving modes is ranked with the others in an order of succession. Accordingly, when each mode of power saving is enabled, it disables the lower-ranked modes of power saving. In turn, each mode of power saving is disabled and succeeded if a higher-ranked mode is enabled.

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Richmond, CA, United States of America

Juraj Bystricky