Samsung Electronics Co., Ltd.

Junyun Kweon

Dongjoon Oh

Hyunsu Hwang

Jumyong Park

Chungsun Lee

Jin Ho An

Solji Song

Jeonggi Jin

Junho Yoon

Yeongbeom Ko

Ju-Il Choi

Heejae Nam

Junggeun Shin

Wooju Kim

YeongBeom Ko

Haemin Park

Suhyeon Ku

A semiconductor device includes a first chip structure including a wiring structure disposed on a circuit elements, and first bonding metal layers and a first bonding insulating layer on the wiring structure, an upper surface of the first chip structure having an edge region and an inner region surrounded by the edge region, a second chip structure disposed on an inner region of the upper surface of the first chip structure, and including second bonding metal layers respectively bonded to the first bonding metal layers, a second bonding insulating layer bonded to the first bonding insulating layer, and a memory cell layer on the second bonding metal layers and the second bonding insulating layer, an insulating capping layer disposed on an upper surface of the second chip structure and extending to the edge region, and a connection pad disposed on a region of the insulating capping layer.

Semiconductor device and method of manufacturing the same

Disclosed are wafer structures and semiconductor devices. A semiconductor device may include a substrate and a cell array structure on the substrate. The substrate may include a device region and a dummy region surrounding the device region in a plan view. The cell array structure may include a plurality of first dielectric layers, a plurality of gate structures, a vertical channel structure, and a dummy pattern. The vertical channel structure may be on the device region and may penetrate the plurality of gate structures and the plurality of first dielectric layers. The cell array structure includes an outer sidewall above an edge of the substrate and a recessed portion on the outer sidewall of the cell array structure. The dummy pattern may cover a sidewall of the recessed portion and a bottom surface of the recessed portion. The dummy pattern and vertical channel structure may include a same material.

Wafer structure and semiconductor device

Provided is a dry etching apparatus including: a plasma process chamber; an edge ring which is arranged in the plasma process chamber and on which a wafer is mounted; a shadow ring positioned to be spaced apart by a first vertical distance above the edge ring during a plasma etching process of the wafer; an operation unit coupled to the shadow ring and having a lift pin that raises and lowers the shadow ring; a fixing portion having a plurality of fixing pins engaged with the lift pin at different positions to fix a lowering point of the shadow ring; and a distance control unit that controls the fixing portion to determine the first vertical distance, wherein the first vertical distance is determined by a first horizontal distance between the wafer and the edge ring.

Dry etching apparatus and wafer etching system using the same

A semiconductor package, comprising: a first redistribution structure including a first redistribution via; a first package that is on an upper surface of the first redistribution structure and comprises a first pad; a second redistribution structure that is on a lower surface of the first redistribution structure and comprises a second redistribution via; a second semiconductor chip that is between the first redistribution structure and the second redistribution structure and comprises a connection pad; and a vertical connection structure that is between the first redistribution structure and the second redistribution structure, wherein the vertical connection structure is electrically connected to the first redistribution via and the second redistribution via, the connection pad is electrically connected to the second redistribution via, and the first redistribution via is electrically connected to the first pad.

Semiconductor packages and methods of forming the same

Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

Interconnection structure and semiconductor package including the same

A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

Semiconductor package including fine redistribution patterns

A method of manufacturing a semiconductor package, includes forming a mask layer on a wafer, the wafer including a semiconductor substrate and an insulating layer; forming a groove in the semiconductor substrate by performing a first laser grooving process; expanding an opening of the mask layer opened by the first laser grooving process by performing a second laser grooving process; exposing a portion of the insulating layer by removing a portion of the mask layer; and cutting the semiconductor substrate while removing the portion of the insulating layer exposed during the exposing by performing a dicing process.

Growing community of inventors

Cheonan-si, South Korea

Junyun Kweon