Samsung Electronics Co., Ltd.

Hyundai Motor Company

Lg Electronics Inc.

Samsung Sdi Co., Inc.

Kia Motors Corporation

Seoul National University

Sungkyunkwan University

Junyoung Park

Junghwan Choi

Youngdon Choi

Hyunyoon Cho

Eunseok Shin

Ju-Il Choi

Wooyong Lee

Jindo Byun

Gyuho Kang

Bokun Choi

Jongmu Choi

Donghan Kim

Un-Byoung Kang

Jongho Lee

Seunghun Lee

Jungeun Lee

Chanmin Park

Hyunsu Hwang

Sang Joon Kim

Minsoo Kim

Kihuk Lee

Doosuk Kang

Younghoon Son

Jongho Park

Suhwan Kim

Junghun Lee

Jiyoon Park

Junsu Choi

Hyunkee Min

Seungchul Jung

Moonsoo Kim

Joohwan Kim

Seongyu Cho

Hyunah Oh

Heewon Kim

Woocheol Shin

Donghwan Seo

Chanhee Yoon

Yonggyoo Kim

Byeongchan Kim

Seokhyeon Yoon

Heechan Kim

Sungwon Kim

Jonghoon Won

Jaewoo Park

Jinwook Lee

Jin Ho An

Sunkey Lee

Hyejin Kang

Ji Hoon Kang

Young-Hoon Son

Hyunsu Park

Shin Han

Woon Ki Cho

Minsheok Choi

Siyoung Park

Kiyeong Jeong

Yoonmyung Lee

Seok Young Yun

Seonghwan Kim

GunHyung Park

Junho An

Hyun-Yoon Cho

Beomjoon Kwon

Obyoung Kang

Seong-Hoon Bae

Junyeop Jung

Hyeonu Choi

Daero Park

Garam Kim

Sechul Park

Kyoungsu Nam

Hyunsub Rie

Youngjin Ahn

Hyungmin Gi

Taehyuck Kim

Hanhee Cho

Changmok Yang

Inho Jeong

Juchul Yun

Jeongyong Myoung

Dayeong Choi

Myunghan You

Jaeyoel Park

Dong Gu Han

Sewon Jang

A transmitter configured to receive first to N-th data in parallel and sequentially output the first to N-th data in response to first to N-th clock signals having different phases from each other, where N is an integer of at least 2, the transmitter including first to N-th data selectors including a first data selector and a second data selector in correspondence to the first to N-th data, each of the first to N-th data selectors being configured to perform a logical operation on one of the first to N-th data and the first to N-th clock signals and output a plurality of data selection signals, a first pre-driver in correspondence to at least two data selectors among the first to N-th data selectors, the first pre-driver being configured to receive the plurality of data selection signals from the at least two data selectors.

Transmitter, memory device and semiconductor device including the transmitter

An integrated circuit device includes: a semiconductor on insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active areas and a plurality of second fin-type active areas each defined by a plurality of trenches, and extending in a first horizontal direction, in above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures comprising nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas; a plurality of first source/drain regions extending into the SOI substrate layer; and a plurality of second source/drain regions extending into the semiconductor substrate layer. Lower surfaces of the first and second source/drain regions may not be coplanar with each other.

Metal-oxide-semiconductor field effect transistors including a plurality of nanosheets

A semiconductor device includes a phase splitter configured to output a plurality of clock signals having different phases by using a plurality of external clock signals having different phases, a plurality of code generators configured to receive a pair of selection clock signals determined from the plurality of clock signals and to output a phase code corresponding to a phase difference error between the pair of selection clock signals, and a delay circuit configured to at least partly simultaneously adjust at least two of a rising edge and a falling edge of each of the plurality of external clock signals with reference to the phase code during a lock time.

Semiconductor device

In a method of generating a multi-level signal having one of three or more voltage levels that are different from one another, input data including two or more bits is received. A drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed. The output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.

Method of generating a multi-level signal using selective equalization, method of transmitting data using the same, and transmitter and memory system performing the same

An electronic device is disclosed. The electronic device according to the present disclosure includes a body, a neck formed at one side of the body, and a head formed on the neck, wherein the head comprises: a circular part connected to the neck; a protrusion part protruding from one side of the circular part and having a curvature that is greater than a curvature of the circular part; a speaker hole formed at at least one of the circular part and the protrusion part; and a band part formed at the periphery of the speaker hole, and the thickness of the band part may be greater than the thickness of the circular part or the protrusion part around the band part.

Electronic device

An amplifying device includes a main amplifier; a first feedback circuit coupled between an input terminal of the main amplifier and an output terminal of the main amplifier; an input coupling circuit coupled between the input terminal of the main amplifier and a first node; and an amplifying feedback circuit coupled between the output terminal of the main amplifier and the first node, wherein the first feedback circuit and the amplifying feedback circuit are negative feedback circuits.

Amplifying device having high input impedance

A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

Semiconductor package

Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

A semiconductor package device may include a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, which includes including a body portion and a protruding portion extended from the body portion to form a single object, an insulating layer covering a side surface of the body portion, and an outer coupling terminal on the protruding portion. The body portion may have a first diameter in a first direction parallel to the top surface of the redistribution substrate, and the protruding portion may have a second diameter in the first direction, which is smaller than the first diameter. A top surface of the protruding portion may be parallel to the first direction, and a side surface of the protruding portion may be inclined at an angle to a top surface of the body portion.

Semiconductor package device

Integrated circuit devices

According to various embodiments, an electronic device may include a communication circuit operably coupled with an external electronic device and at least one processor, wherein the at least one processor may be configured to determine one or more target-wake-time (TWT) parameters of at least one TWT service period based on at least one of the amount of data transmitted to the external electronic device, an amount of data received from the external electronic device, or a bandwidth, wherein at least one data frame is transmitted or received between the electronic device and the external electronic device during the at least one TWT service period; identify quality of service (QoS) for the at least one data frame transmitted or received during the at least one TWT service period; change at least one TWT parameter among the one or more TWT parameters based on the identified QoS; and control the communication circuit to transmit or receive at least one next data frame during the a next TWT service period based on the changed at least one TWT parameter.

Electronic device performing rescheduling over wireless channel and method for controlling same

A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.

Transmitter circuit and method of operating same

A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.

Transmitter circuit including selection circuit, and method of operating the selection circuit

An electronic device is disclosed herein. The electronic device includes a display, at least one wireless communication circuit configured to perform Wi-Fi wireless communication with at least one access point (AP) and/or at least one external electronic device, a processor operatively connected to the display and the wireless communication circuit, and a memory operatively connected to the processor, wherein the memory stores instructions executable by the processor to cause the electronic device to: execute Wi-Fi scanning and receive a first signal from the at least one AP by the wireless communication circuit, receive a second signal from the at least one external electronic device by the wireless communication circuit, the second signal including information related to the at least one AP, determine a wireless communication channel state of the AP based at least partially on the first signal and the second signal, and control the display to display a graphic user interface (GUI) including an object indicating the determined wireless communication channel state.

Electronic device and method for operating access point information by electronic device

A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals. The second inverting circuit is configured to adjust a second delay time for the first edge, the second edge, or both of the first edge and the second edge of the clock signal.

Delay circuit and clock error correction device including the same

Growing community of inventors

Suwon-si, South Korea

Junyoung Park