Samsung Electronics Co., Ltd.

Junyoung Ko

Changhwi Park

Jungmin Bak

Sangwan Nam

Jaeyong Park

Whasu Sin

Kyhyun Jung

Chaehoon Kim

Young-Ja Kim

Minjae Seo

Hojun Lee

Jiwon Seo

Daesang Chan

Heewon Kim

Jiyeon Han

Young-ja Kim

Chansik Kwon

Jinduck Park

Youse Kim

Jongkeun Moon

Senyun Kim

Younghoon Ro

A CXL device includes at least one memory; a CXL controller configured to receive a request to access the at least one memory via a CXL interface, and to output a memory identifier indicating a first memory of the at least one memory, a command and a row address of the first memory based on the request; and a refresh controller configured to store the row address as a target row address of the first memory and further configured to generate a targeted refresh signal based on a number of receptions of the command for refreshing the target row address in the first memory.

CXL device and operation method of CXL device

A memory device includes a memory cell array including a plurality of memory cells, a word line defect detection circuit electrically connected to the memory cell array through a plurality of word lines, and control logic configured to control an input/output operation of the memory cell array. When a memory defect detection command is received from a memory controller, the word line defect detection circuit is configured to provide an input voltage to a selected word line among the plurality of word lines, and to generate a fail flag based on a difference between a voltage of the selected word line and a reference voltage. When a mode register read command is received from the memory controller, the control logic is configured to transmit the fail flag and a fail row address corresponding to the fail flag to the memory controller.

Memory device included in memory system and method for detecting fail memory cell thereof

A test device includes a power supply circuit that is configured to supply an input voltage through a power voltage pin to a memory device under test, and a test controller, which is configured to: (i) transmit a command signal to the memory device, (ii) measure a first current flowing to the memory device through the power voltage pin at a first time point after transmitting the command signal, (iii) measure a second current flowing to the memory device through the power voltage pin at a second time point, which is different from the first time point, and (iv) compare the measured first current to the measured second current to thereby determine whether the memory device has a defect therein.

Test devices and systems that utilize efficient test algorithms to evaluate devices under test

A row decoder circuit includes a first transistor connected to a power supply node and a first node; a plurality of second nodes connected in parallel between the first node and a power ground node, each of the plurality of second nodes being connected to a corresponding word line among the plurality of word lines; a plurality of second transistors connected between the first node and the plurality of second nodes; a plurality of third transistors connected between the plurality of second nodes and a power ground node; a comparator outputting a detection signal by receiving a voltage of the first node and a reference voltage. In a pre-charging period, the first transistor is turned on, the plurality of second transistors are turned on, and the third transistors are turned off, so that the first node and the plurality of second nodes are charged. In a development period, the first transistor maintains a turned-on state, the plurality of second transistors are turned off, and each of the second nodes is discharged at a different rate depending on whether current of the corresponding word line is leaked, and in a sensing period, the first transistor is turned off, the plurality of second transistors are turned on, and the first node is selectively discharged according to voltage levels of the discharged second nodes.

Row decoder circuit, memory device and memory system

A semiconductor device may include: a memory device that includes a memory cell, a page buffer, and a first switch having a first end that is electrically connected to a first node located at a bonding point of the memory cell and a second end that is connected to a second node located at the page buffer; and a memory controller that is configured to apply a pre-charge voltage to the first node and the second node in a first period, to close the first switch in a second period following the first period, and is configured to determine whether bonding between the memory cell and the first switch is defective based on a voltage of the second node after the first switch is closed.

Bonding defect detection for die-to-die bonding in memory devices

A volatile memory device includes an array of memory cells connected to word lines, and bit lines, which are connected to a bitline sense amplifier. Control logic is provided, which is configured to control: (i) consecutive self-refresh operations within the array of memory cells, (ii) storage of dummy data within the array of memory cells during operations to predict life expectancy of memory cells therein, (iii) consecutive test refresh operations within the array of memory cells, and (iv) performance of test sensing operations on selected memory cells within the array using the bitline sense amplifier. A deterioration detection circuit is provided, which is configured to receive sensing results associated with the selected memory cells from the bitline sense amplifier.

Volatile memory devices and methods of operating same to improve reliability

A defense method of a memory device according to an embodiment includes obtaining a plurality of defense types to refresh a row of a memory cell array that is subjected to an attack, determining respective operation times for the defense types, and performing a refresh operation for the row of the memory cell array by switching among the defense types based on the respective operation times that were determined.

Memory device and defense method thereof

A memory device may include a time counter which is configured to output a count signal according to a predetermined time interval; a use history circuit which is configured to write an operating time value based on the count signal and generate and write a validation value corresponding to the operating time value; and a command decoder which is configured to receive an instruction from a memory controller. The instruction may be according to an operation mode that is determined based on the operating time value and the validation value.

Memory devices and methods for managing use history

Provided is a non-volatile memory device. The non-volatile memory device includes: a memory cell array including cell strings, each including memory cells respectively connected to word lines; a page buffer circuit including page buffers respectively connected to the memory cells through bit lines, wherein a first page buffer is connected to a first cell string through a first bit line; a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string to each other in a post-sensing period for detecting defects of the word lines and the first bit line; and a defect detection circuit configured to detect defects of the word lines based the sensing operations.

Non-volatile memory device for detecting defects of bit lines and word lines

A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.

Nonvolatile memory device and method of operating a nonvolatile memory

A test apparatus includes a test chamber in which a plurality of the semiconductor packages having a plurality of component dies is secured, an operation tester configured to conduct an operation test to the plurality of semiconductor packages to detect whether at least one semiconductor package is an operation fault package having a fault and identify a fault package point at which the operation fault package is located, a fault heat detector configured to detect a fault heat generated from the fault, and a test controller configured to control the operation tester to conduct the operation test to the plurality of semiconductor packages and control the fault heat detector subsequent to the operation test to detect the fault heat generated from the fault of the operation fault package to determine a vertical point of the fault and to determine a fault die having the fault.

Test apparatuses for testing semiconductor packages and manufacturing systems for manufacturing semiconductor packages having the same and methods of manufacturing the semiconductor packages using the same

A semiconductor device comprises a substrate, a semiconductor chip on the substrate, and first and second leads between the substrate and the semiconductor chip. The first and second leads extend from an edge of the substrate toward below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first lead includes a first bump connector and a first segment. The second lead includes a second bump connector. The first bump connector is spaced apart in the first direction from the second bump connector. The first segment of the first lead is spaced apart in a second direction from the second bump connector. The second direction is parallel to the top surface of the substrate and perpendicular to the first direction. A thickness of the first segment of the first lead is less than that of the second bump connector.

Semiconductor devices

A removal apparatus for a semiconductor chip may include a stage configured to support a board on which the semiconductor chip is mounted by bumps, a laser configured to irradiate a laser beam into the board over an area larger than the semiconductor chip, and a picker configured to cause the laser beam to penetrate the semiconductor chip locally and to separate the semiconductor chip from the board. A method of removing a semiconductor chip from a board may include loading the board, on which the semiconductor chip is mounted by bumps, on a stage; irradiating a laser beam into the semiconductor chip to melt the bumps and to separate the semiconductor chip from the board; continuously irradiating the laser beam into the board on which solder pillars, that are residues of the bumps, remain to melt the solder pillars; and removing the solder pillars.

Removal apparatuses for semiconductor chips

Embodiments of inventive concepts disclosed provide a method of manufacturing a semiconductor package. The method includes mounting a plurality of semiconductor chips on a substrate having a connecting member protruding from a top surface of the substrate, applying a non-conductive paste on the substrate and the semiconductor chips, forming a supporting layer coupling each of the semiconductor chips to the substrate, aligning an interposer on the non-conductive paste, forming a non-conductive layer by applying heat while pressing the interposer and the substrate against each other, and cutting the substrate, the non-conductive layer, and the interposer into separate unit packages, each of which include a semiconductor chip.

Growing community of inventors

Cheonan-si, South Korea

Junyoung Ko