Samsung Electronics Co., Ltd.

Junyoung Jeong

Seungjae Lee

Hyunchang Shin

Bowon Jung

Namhyeon Jeon

Gyudong Eom

Sungwon Ryu

Jung Woon Lee

Hyojun Koo

Jihan Lee

Soonwoo Choi

A computing system configured to verify design of an integrated circuit (IC) includes a memory and a processor. The memory is configured to store computer executable instructions. The processor is configured to generate a first coverage model for at least two high-level parameters from the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard or hardware description language (HDL) code by executing the computer executable instructions, generate a second coverage model for low-level internal signals from the HDL code by executing the computer executable instructions, and generate a plurality of test packets for a regression test by using at least one of the first coverage model or the second coverage model by executing the computer executable instructions.

Computing system and method of verifying circuit design in computing system

This electronic device comprises: a window comprising a first region; a display panel comprising a first opening; an adhesive member comprising an adhesive material and comprising a second opening; an opaque member comprising an opaque material disposed along the boundary of the first region; a sensor disposed under the window and visible through the first and second openings; and a display driving circuit configured to activate some first pixels among the pixels of the display panel disposed in a region where the display panel overlaps the opaque member.

Electronic device and method for controlling pixels adjacent to sensor arranged inside display, and computer readable medium

Provided is an OFDM receiver which extracts a time sync signal from a prefix having a symmetric structure. The OFDM receiver, according to exemplary embodiments of the present invention, generates the sync signal (e.g., start point) of a symbol by using only the MSB (e.g., sign bit) of the cyclic prefix of an OFDM symbol, reducing the overhead of a logic circuit for generating the sync signal of the symbol.

Orthogonal frequency division multiplexing receiver

Growing community of inventors

Suwon-si, South Korea

Junyoung Jeong