Sanechips Technology Co., Ltd.

Southern University of Science and Technology

Junyi Yang

Xuewei Ding

Wenbo Xiao

Quan Pan

Qiwei Huang

Yingli Hao

A clock data recovery circuit and a clock data recovery method are provided. The clock data recovery circuit includes a time delay loop (), a frequency locking loop () and a deserializer (). The time delay loop () is configured to delay input data according to a phase of a clock signal to realize phase alignment; the frequency locking loop () is connected to the time delay loop (), and is configured to adjust a frequency of the clock signal according to the delayed input data to make the frequency of the clock signal be consistent with a frequency of the input data; and the deserializer () is respectively connected to the time delay loop () and the frequency locking loop (), and is configured to deserialize the input data according to the clock signal.

Growing community of inventors

Guangdong, China

Junyi Yang