Samsung Electronics Co., Ltd.

Junyeon Won

Shinki Jeong

A test device includes a comparison circuit configured to receive a plurality of input signals and generate a plurality of comparison signals based on the plurality of input signals; and a field programmable gate array (FPGA) configured to recover clock data, based on the plurality of comparison signals, wherein the FPGA includes a sampling circuit configured to generate a plurality of sample data signals by sampling the plurality of comparison signals; an edge extraction circuit configured to generate a plurality of edge data signals, based on logic values of bits in the plurality of sample data signals; an edge combining circuit configured to generate combined edge data by performing a logic operation on the plurality of edge data signals; and a filter circuit configured to recover the clock data by filtering the combined edge data.

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Seoul, South Korea

Junyeon Won