Yangtze Memory Technologies Co., Ltd.

Junyao Zhu

Xueqing Huang

Jing Wei

Jinlong Zhang

Lu Qiu

Yao Chen

Jianyu Xiang

Yuankang Yang

Qingqi Li

Example memory devices, systems, and methods for reducing erase disturb in memory devices are disclosed. One example method includes erasing, during an erase operation of a block in a memory cell array, one or more memory cells in the block. It is verified, during the erase operation of the block, whether the one or more memory cells are erased. Each of one or more blocks in the memory cell array is respectively read during the erase operation of the block, where respectively reading each of the one or more blocks includes applying a first voltage to a first select gate line coupled to a first select gate transistor in the block, and applying a second voltage to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, where the first voltage is lower than the second voltage.

Erase operations in memory devices

A memory includes at least a target word line and a first word line group and a second word line group respectively stacked on both sides of the target word line. The first word line group includes first word lines, and the second word line group includes second word lines. A method for operating the memory includes, during a pre-charge operation, applying a first bias voltage signal to the plurality of first word lines, applying a second bias voltage signal to a target word line, and applying a third bias voltage signal to the plurality of second word lines. The method also includes, during a programming operation, applying a program voltage signal to a target word line.

Operation method of memory, memory, memory system, and electronic device

Growing community of inventors

Wuhan, China

Junyao Zhu