Micron Technology Incorporated

Junya Suzuki

Hiroshi Ichikawa

Hidenori Yamaguchi

Katsumi Koge

An apparatus includes a substrate, a memory cell region provided over the substrate, a peripheral region provided over the substrate and adjacent to the memory cell region, and first, second, third, fourth and fifth word-lines each extending in parallel across the memory cell region and the peripheral region in numerical order. An offcut of the second word-line is interposed between edge portions of the first and third word-lines, and no offcut of the fourth word-line is interposed between edge portions of the third and fifth word-lines.

Semiconductor memory device having the structure of word-lines to avoid short circuit and method of manufacturing the same

A semiconductor device includes: a substrate; a memory cell region over the substrate; a peripheral region over the substrate, the peripheral region being adjacent to the memory cell region; and a plurality of first and second word-lines extending across the memory cell region and the peripheral region; wherein the plurality of first word-lines and the plurality of second word-lines are arranged alternately with each other; and wherein the length of the first word-line in the peripheral region is longer than the length of the second word-line in the peripheral region.

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Higashihiroshima, Japan

Junya Suzuki