Qualcomm Incorporated

Other

Marvell International Limited

Marvellworld Trade Ltd.

Marvell Semiconductor, Inc.

Junxiong Deng

Aleksandar Miodrag Tasic

Gurkanwal Singh Sahota

Taotao Yan

Bhushan Shanti Asuri

Aristotele Hadjichristos

Frederic Bossu

Prasad S Gudem

Christian Holenstein

Zhang Jin

Maulin Pareshbhai Bhagat

Namsoo Kim

Dongjiang Qiao

Hongyan Yan

Zhigang Xu

Manas Behera

Vladimir Aparin

Li Liu

Chinmaya Mishra

Prashanth Akula

Thomas Domenick Marra

Thomas Myers

Guy Klemens

Solti Peng

Mohammad Farazian

Ockgoo Lee

Yanping Ding

Peichen Jiang

Norman L Frederick

Aspects of the disclosure provide an operational transconductance amplifier (OTA) having an output stage. The output stage includes a first amplifier path configured to drive a first output current from a first power supply and a first resistor coupled between the first power supply and a source terminal of a first transistor in the first amplifier path. The first resistor is configured to improve a linearity of the OTA.

Operational transconductance amplifier of improved linearity

Aspects of the disclosure provide a circuit having a filter circuit and a controller. The filter circuit drives a load circuit having different input impedances under different operation conditions. The filter circuit is configured to have a first output circuit coupled with a first resistor and a second output circuit coupled with a second resistor. The controller is configured to generate control signals to select one of the first output circuit and the second output circuit based on an operation condition of the load circuit.

Method and apparatus to reconfigure a filter

System and methods are provided for reducing signal distortion in wireless communication. An example system includes: an up-converter configured to generate a radio frequency signal based at least in part on a baseband signal for wireless communication and an oscillation signal; an amplifier configured to amplify the radio frequency signal and generate a transmission signal, the transmission signal including a first counter-intermodulation component associated with the up-converter and a second counter-intermodulation associated with the amplifier; and a signal generator configured to output a distortion-cancellation signal to the up-converter to reduce signal distortion associated with the first counter-intermodulation component and the second counter-intermodulation component.

Systems and methods for reducing signal distortion in wireless communication

An adaptable mixer device is operable in a first mode and a second mode and includes a first set of mixer units operable in the first mode and a second set of mixer units operable in the second mode. The second set of mixer units includes at least one mixer unit that is common to both the first set of mixer units and the second set of mixer units. The second set of mixer units also includes a plurality of mixer units that are not in the first set of mixer units. Similarly, the first set of mixer units including a plurality of mixer units that are not in the second set of mixer units.

Adaptable mixer and local oscillator devices and methods

A current mirror circuit is described. The current mirror circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are coupled at a bias voltage. The current mirror circuit also includes an auxiliary transistor that is biased into weak inversion by receiving the bias voltage at a gate of the auxiliary transistor after being reduced by an offset voltage. The sources of the first transistor, second transistor and auxiliary transistor are coupled together. A primary current from the drain of the second transistor is combined with an auxiliary current from the drain of the auxiliary transistor to produce an output current.

Canceling third order non-linearity in current mirror-based circuits

A method for reducing average current consumption in a local oscillator (LO) path is disclosed. An LO signal is received at a master frequency divider and a slave frequency divider. Output from the master frequency divider is mixed with an input signal to produce a first mixed output. Output from the slave frequency divider is mixed with the input signal to produce a second mixed output. The second mixed output is forced to be in phase with the first mixed output.

Systems and methods for reducing average current consumption in a local oscillator path

An exemplary embodiment disclosed comprises a mixer having a plurality of input leads; a first degenerative impedance element coupled to a first input lead of the mixer; a second degenerative impedance element coupled to a second input lead of the mixer; and a local oscillator (LO) system comprising a plurality of duty cycle modes to generate a LO signal for the mixer, the local oscillator system operates in a first duty cycle based on a first gain state of the mixer, and in a second duty cycle based on a second gain state of the mixer.

Reduced power-consumption receivers

An integrated circuit is described. The integrated circuit includes an inductor that has a large empty area in the center of the inductor. The integrated circuit also includes additional circuitry. The additional circuitry is located within the large empty area in the center of the inductor. The additional circuitry may include a capacitor bank, transistors, electrostatic discharge (ESD) protection circuitry and other miscellaneous passive or active circuits.

Methods and apparatus for inductors with integrated passive and active elements

An exemplary embodiment discloses a digital control block for dynamically regulating power consumption of the transmitter; and a first driver amplifier circuit comprising a plurality of bias-modes each corresponding to a power consumption level in the transmitter, the digital control block to instruct the first driver amplifier circuit to operate in a selected bias-mode to regulate power consumption of the transmitter.

Reduced power-consumption transmitters

Disclosed are circuits, techniques and methods for removing one or more harmonics from a waveform that has been mixed with a local oscillator. In one particular example, such a waveform may also be mixed with a second local oscillator at a different frequency and combined with the first mixed waveform to suppress and/or substantially remove the one or more harmonics.

Harmonic suppression and/or rejection

A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circuit supplies a feedback signal onto the first dynamic-flop of the chain. In a first mode, a signal from a slave stage of the first flip-flop and a signal from a slave stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. In a second mode, a signal from a master stage of the first flip-flop and a signal from a master stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. By proper selection of the mode, the frequency range of the overall divider is extended. Combinatorial logic converts thirty-three percent duty cycle signals from the flip-flop chain into fifty percent duty cycle quadrature signals.

Differential quadrature divide-by-three circuit with dual feedback path

A circuit is described. The circuit includes a low noise amplifier (LNA), a passive switching core (PSC), a transimpedance amplifier filter (TIA-filter) and a degenerative-impedance gain-tuning network (Zdeg network) having a first Zdeg network input lead, a second Zdeg network input lead, a first Zdeg network output lead and a second Zdeg network output lead, wherein the first Zdeg network input lead is coupled to a first output lead of the LNA and the second Zdeg network input lead is coupled to a second output lead of the LNA, and wherein the first Zdeg network output lead is coupled to a first signal input lead of the PSC and the second Zdeg network output lead is coupled to a second signal input lead of the PSC. The LNA, the Zdeg network, the PSC, and the TIA-filter together form a receiver. A receiver gain is adjusted by the Zdeg network.

Systems and methods for adjusting the gain of a receiver through a gain tuning network

A multi-mode low noise amplifier (LNA) with transformer source degeneration is described. In an exemplary design, the multi-mode LNA includes first, second, and third transistors and first and second inductors. The first transistor has its source coupled to the first inductor, amplifies an input signal, and provides a first amplified signal in a first mode. The second transistor has its source coupled to the second inductor, amplifies the input signal, and provides a second amplified signal in a second mode. The third transistor has its source coupled to the second inductor. The first and third transistors receive the input signal and conduct current through the first and second inductors, respectively, in a third mode. The first transistor observes source degeneration from a transformer formed by the first and second inductors, amplifies the input signal, and provides a third amplified signal in the third mode.

Multi-mode low noise amplifier with transformer source degeneration

A transmitter includes a transformer and a transformer tuning circuit. The transformer transforms a differential radio frequency (RF) signal to a single-ended RF signal. The transformer tuning circuit tunes the transformer to permit the transmitter to transmit the single-ended RF signal in a first frequency band (e.g., cellular frequency band) or a second frequency band (e.g., PCS frequency band).

Dual band radio frequency transmitter

A complementary amplifier includes an NMOS transistor coupled to a PMOS transistor in a stacked configuration. The NMOS transistor and the PMOS transistor receive and amplify an input signal. The NMOS and PMOS transistors operate as a linear complementary amplifier and provide an output signal. The NMOS and PMOS transistors may have separate bias voltages, which may be selected to overlap the low-to-high and high-to-low transitions of the transconductances of these transistors. The width and length dimensions of the NMOS and PMOS transistors may be selected to match the change in input capacitance and the change in transconductance of the NMOS transistor in moderate inversion region with the change in input capacitance and the change in transconductance of the PMOS transistor in moderate inversion region. The complementary amplifier may have an approximately constant total input capacitance and an approximately constant total transconductance over a range of voltages.

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San Diego, CA, United States of America

Junxiong Deng