Samsung Electronics Co., Ltd.

Junwoo Lee

Sungdong Cho

Wonsuk Jung

Yonghyeok Son

Junghoon Han

Juik Lee

Jihoon Chang

Jintae Jang

Joongwon Shin

Jangsub Yi

An example electronic device may include a storage device including a device interface and a non-volatile memory; an interface including a plurality of transmitting lanes and a plurality of receiving lanes and configured to communicate with the storage device; and at least one processor configured to control processing of data through the interface based on an input/output request generated by an application, wherein one or more of the at least one processor may process the data through a first group of lanes when the input/output request indicates data write; process the data through a second group of lanes, in which more lanes than the first group of lanes are enabled, when the input/output request indicates data read; and process the data through the second group of lanes when the amount of resources of the electronic device used while the data is processed through the first group of lanes exceeds a designated level.

Data processing system and operation method of data processing apparatus

A host for managing a storage device is provided. The host includes a storage host interface configured to communicate with the storage device comprising a cache and a non-volatile memory and at least one processor. The at least one processor may be configured to receive information indicating cache loss from the storage device after device reset of the storage device, suspend a data input/output operation for the storage device, transmit a buffer read command to the storage device, and receive cache information related to data remaining in the cache without being stored in the non-volatile memory before the device reset from the storage device in response to the buffer read command.

Apparatus for managing cache loss and operation method thereof

A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

Semiconductor memory device including wiring contact plugs

The various embodiments disclose an electronic device including: a storage including a non-volatile memory having a buffer space and a storage space, a storage device controller, and a storage interface, and a processor. According to various embodiments, the processor may be configured to perform control to determine whether the storage supports a high speed data storage mode using a buffer space of a non-volatile memory of the storage, activate a function of writing data buffered in the buffer space of the non-volatile memory into a storage space of the non-volatile memory based on the storage interface operating in a first state based on the storage supporting the high speed data storage mode, and transition the storage interface of the storage to the first state based on no request to the storage being generated during a predetermined time period based on the storage interface operating in a second state.

Electronic device and method of utilizing storage space thereof

A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.

Growing community of inventors

Bucheon-si, South Korea

Junwoo Lee