International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Elpis Technologies Inc.

Samsung Electronics Co., Ltd.

Adeia Semiconductor Solutions LLC

Tessera LLC

Stmicroelectronics Gmbh

Canon Anelva Corporation

Juntao Li

Kangguo Cheng

Peng Xu

Choonghyun Lee

Ruilong Xie

Zhenxing Bi

Geng Wang

Shogo Mochizuki

Chanro Park

Chih-Chao Yang

Qintao Zhang

Hong He

Xin Miao

Junli Wang

Dexin Kong

Heng Wu

Carl John Radens

Ramachandra Divakaruni

Ali Khakifirooz

Chengwen Pei

Veeraraghavan S Basker

Takashi Ando

Joseph Ervin

Chen Zhang

Julien Frougier

Yunpeng Yin

Fee Li Lie

Zuoguang Liu

Devendra K Sadana

Chun-chen Yeh

Jeehwan Kim

John Gerard Gaudiello

Bruce Bennett Doris

Tenko Yamashita

Sivananda K Kanakasabapathy

Zheng Xu

Sanjay C Mehta

Gauri V Karve

Yi Song

Son Van Nguyen

James J Demarest

Thomas J Haigh, Jr

Alexander Reznicek

Dechao Guo

Balasubramanian Pranatharthiharan

Hsueh-Chung Chen

Qing Cao

Eric Gerhard Liniger

ChoongHyun Lee

Arthur Gasasira

Daniel C Edelstein

Shom Ponoth

Takeshi Nogami

Cyril Cabral, Jr

John Ryan Sporre

Chun Wing Yeung

Stuart A Sieg

Huimei Zhou

Hao Tang

Derrick Liu

Liying Jiang

Brent A Anderson

Nicolas J Loubet

Jingyun Zhang

Praneet Adusumilli

Robert Russell Robison

Oscar Van Der Straten

Ekmini Anuja De Silva

Andrew Mark Greene

Thomas N Adam

Ravi Mahendra Todi

Tao Li

Tsung-Sheng Kang

Ching-Tzu Chen

Guy M Cohen

Oleg Gluschenkov

Michael Rizzolo

Ruqiang Bao

Reinaldo Ariel Vega

Xiuyu Cai

Min Gyu Sung

Amlan Majumdar

Zhen Zhang

Yu Zhu

Vamsi Krishna Paruchuri

Richard Anthony Conti

Pierre Morin

Paul Charles Jamison

Kevin W Brew

Michael P Belyansky

Vimal Kumar Kamineni

Lan Yu

Werner A Rausch

Jody Alan Fronheiser

Ardasheir Rahman

Adra Carr

Tuan Anh Vo

Sebastian Naczas

Sung Dae Suk

A semiconductor structure includes a substrate disposed in a horizontal plane, a gate metal on the substrate, a first spacer and a second spacer on the substrate with the gate metal between the first spacer and the second spacer, and a plurality of horizontally stacked nanosheets extending between the first spacer and the second spacer, with the gate metal encapsulating the plurality of horizontally stacked nanosheets between the first spacer and the second spacer.

Horizontally stacked nanosheet gate all around device structure

A phase change memory includes a phase change structure. There is a heater coupled to a first surface of the phase change structure. A first electrode is coupled to a second surface of the phase change structure. A second electrode coupled to a second surface of the heater. A third electrode is connected to a first lateral end of the phase change structure and a fourth electrode connected to a second lateral end of the phase change structure.

Multi-level programming of phase change memory device

A device structure for a phase-change memory device is disclosed. The device structure includes a top electrode, a phase-change material that is recessed between two layers of resistive liner material, and a conductive material. The conductive material contacts the sidewall of the top electrode, the sidewall of the phase-change material, and a portion of a top surface and a bottom surface of each of the two layers of the resistive liner material. The device structure includes a heater contacting a bottom electrode and the bottom layer of the resistive liner material. The heater is in a first bilayer dielectric. A second bilayer dielectric is under the top electrode.

Phase-change memory device with conductive cladding

An integrated circuit (IC) is provided. The IC includes a substrate that includes first and second channels. A shared source or drain (S/D) region is between the first and second channels. The shared source or drain region includes an uppermost surface and further includes a second surface recessed from the uppermost surface and sidewalls extending from the uppermost surface to the second surface to define a recess. First and second gate structures including gate metal are disposed on the first and second channels. An S/D wrap-around contact (WAC) includes a first portion which extends into the recess to contact the second surface and the sidewalls and is wrapped around the S/D region at an exterior of the recess.

Non-self-aligned wrap-around contact in a tight gate pitched transistor

A stacked semiconductor device includes a lower semiconductor device that has a backside and includes a flipped upper semiconductor device that has a backside that is opposed to the lower semiconductor device backside. The flipped upper semiconductor device further includes a backside residual semiconductor on insulator (SOI) layer and a stressed dielectric portion thereupon. The stacked semiconductor device may be formed by stacking and bonding the flipped upper semiconductor device to the lower semiconductor device, removing one or more semiconductor on insulator (SOI) layers from the backside of the flipped upper semiconductor device while retaining an exposed backside residual SOI layer of the flipped upper semiconductor device, forming a stressed dielectric layer upon the exposed backside residual SOI layer, and patterning the stressed dielectric layer.

Vertically stacked FET with strained channel

A stacked phase change memory structure having a cross-point architecture is provided. The stacked phase change memory structure includes at least two phase change material element-containing structures stacked one atop the other. Each phase change material element-containing structure of the plurality of phase change material element-containing structures has a cross-point architecture and includes, from bottom to top, at least one bottom electrode, a phase change material element, and a top electrode.

Stacked cross-point phase change memory

A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

Stressed material within gate cut region

A method including forming a plurality of nanosheet layers on a substrate and forming a plurality of first sacrificial layers on the substrate, wherein the plurality of nanosheet layers and the plurality of first sacrificial layers are arranged in alternating layers, where the plurality of first sacrificial layers is comprised of a first material. Selectively removing the plurality of first sacrificial layers and forming a plurality of second sacrificial layers where the plurality of first sacrificial layers were removed, where the plurality of second sacrificial layers is comprised of a second material, where the first material and the second material are different. Recessing the plurality of second sacrificial layers at an even rate.

Method to release nano sheet after nano sheet fin recess

Semiconductor devices, and methods of forming the same, include forming a stack of channel layers, including an upper device region and a lower device region. The upper device region is separated from the lower device region by a dielectric spacer layer. A first work function metal layer is formed on the channel layers in the lower device region. A height of the first work function metal layer does not rise above the dielectric spacer layer. A second work function metal layer is formed on the channel layers in the upper device region.

Work function metal patterning for nanosheet CFETs

A method for forming a semiconductor device includes forming a structure having at least a first nanosheet stack for a first device, a second nanosheet stack for a second device and disposed over the first nanosheet stack, a disposable gate structure, and a gate spacer. The disposable gate structure and sacrificial layers of the first and second nanosheet stacks are removed thereby forming a plurality of cavities. A conformal gate dielectric layer is formed in the plurality cavities and surrounding at least portions of the first and second nanosheet stacks. A first conformal work function layer is formed in contact with the gate dielectric layer. Portions of the first conformal work function layer are removed without using a mask from at least the second nanosheet stack. A second conformal work function layer is formed on exposed portions of the gate dielectric layer.

Vertical stacked nanosheet CMOS transistors with different work function metals

The density of deuterium or hydrogen within phase change material (PCM) of a PCM memory cell reduces the active defects in the amorphous phase of the PCM by passivating dangling bonds, which results in the PCM becoming easier to nucleate during the SET process of the PCM memory cell. Resultingly, the addition of deuterium or hydrogen within the PCM relatively increases the SET programming voltage window of the PCM memory cell compared with a similar PCM cell without.

Phase change material including deuterium

Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

Nanosheet transistor

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a dynamic random-access-memory (DRAM), and the DRAM includes a vertical transistor and a nanosheet transistor, the vertical transistor being stacked on top of the nanosheet transistor, where a bottom source/drain of the vertical transistor is directly above and connected to a gate of the nanosheet transistor through a conductive via. A method of manufacturing the semiconductor structure is also provided.

Scaled 2T DRAM

Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an Mlevel including an Mmetal in an Mdielectric, an Mlevel above the Mlevel including an Mmetal in an Mdielectric, an embedded diffusion barrier adjacent to the Mdielectric; and a seed alloy region adjacent to the Mmetal separating the Mmetal from the Mmetal. The embedded diffusion barrier may include a barrier-forming material such as manganese, aluminum, titanium, or some combination thereof. The seed alloy region may include a seed material such as cobalt, ruthenium, or some combination thereof.

Self-forming embedded diffusion barriers

A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.

Replacement gate cross-couple for static random-access memory scaling

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Cohoes, NY, United States of America

Juntao Li