Electronics and Telecommunications Research Institute

Junsoo Ko

Cheon Soo Kim

Ja Yol Lee

Minjae Lee

Jaehyun Kang

Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.

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Namyangju-si, South Korea

Junsoo Ko