Nippondenso Co., Ltd.

Junsi Utsu

Masao Kodera

Seishin Mikami

Series reactance elements constituted by capacitors are connected to an input side corresponding to the gate electrode of an amplifying FET and an output side corresponding to the drain electrode of the amplifying FET, respectively. Parallel variable reactance circuits are connected to the input and output sides, respectively. Each variable reactance circuit includes a FET, where the source electrodes of the FET are connected to the input and output sides through MIM capacitors, respectively. Additionally, drain electrodes of the FETs are grounded through inductive loads which are constituted by spiral inductors, respectively. The source electrodes of the FETs constituting the variable reactance circuits are grounded through choke coils, respectively. The drain electrodes of the FETs receive control bias voltages through the choke coils, respectively. In this case, each of the resistive components of the spiral inductors is set to have a value which can cancel the negative resistive component of the corresponding FET.

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Oobu, Japan

Junsi Utsu