Credo Technology Group Limited

Junqing (Phil) Sun

Haoli Qian

Fang Cai

Yasuo Hidaka

Yu Liao

Tianchen Luo

Accordingly, there are disclosed herein receivers and receiving methods that provide a graceful transition from PAM2 to PAM4 signaling. One illustrative method includes: negotiating a link speed having PAM4 signaling; performing adaption of at least one gain or filter coefficient during PAM2 signaling; switching to PAM4 detection before receiving PAM4 signaling; disabling said adaptation before said switching to PAM4 detection; detecting PAM4 signaling using at least one statistic of detected PAM4 symbols; and enabling said adaptation after PAM4 signaling is detected. Another illustrative method includes: negotiating a link speed having PAM4 signaling; adapting at least one of gain and filter coefficients during PAM2 signaling; monitoring for a change in at least one signal characteristic while performing PAM2 detection; and transitioning to PAM4 detection after detecting said change.

Transitioning between signal constellations

Reduced-complexity maximum likelihood sequence detectors (rMLSD) are disclosed for detecting multibit symbols such as those found in pulse amplitude modulation (PAM), quadrature amplitude modulation (QAM), and phase shift keying (PSK) signal constellations with more than two constellation points. One illustrative digital communications receiver includes: an initial equalizer that derives an initial sequence of symbol decisions from a filtered receive signal, each symbol decision in the initial sequence having a second most likely symbol decision; and a rMLSD that derives a final sequence of symbol decisions by evaluating state metrics only for each symbol decision in the initial sequence and its second most likely symbol decision.

Reduced-complexity maximum likelihood sequence detector suitable for m-ary signaling

An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.

Receiver with threshold level finder

Equalization methods and equalizers employing discrete-time filters are provided with dynamic perturbation effect based adaptation. Tap coefficient values may be individually perturbed during the equalization process and the effects on residual ISI monitored to estimate gradient components or rows of a difference matrix. The gradient or difference matrix components may be assembled and filtered to obtain components suitable for calculating tap coefficient updates with reduced adaptation noise. The dynamic perturbation effect based updates may be interpolated with precalculated perturbation effect based updates to enable faster convergence with better accommodation of analog component performance changes attributable to variations in process, supply voltage, and temperature.

Equalizer with perturbation effect based adaptation

One illustrative equalizer converts a receive signal into a sequence of symbol decisions using: a linear filter that filters the receive signal as part of deriving a first sequence of equalized signal samples; a first decision element that derives a tentative sequence of symbol decisions from the first sequence of equalized signal samples; a nonlinear filter that, when enabled, applies nonlinear compensation to the linearly filtered receive signal as part of deriving a second sequence of equalized signal samples; a second decision element that, when enabled, derives replacement symbol decisions from the second sequence of equalized signal samples; a subtraction element that calculates an equalization error for each symbol decision in the tentative sequence; and a controller that selectively enables the nonlinear filter and the second decision element to obtain a replacement symbol decision for each symbol decision in the tentative sequence having an equalization error greater than a predetermined value.

Power-efficient nonlinear equalizers and methods

An illustrative short, high-rate communications link includes a serializer that provides a signal having a symbol rate of at least 10 GHz; and a deserializer that receives the signal via a printed circuit board ('PCB') trace coupled to the serializer with a first impedance mismatch and coupled to the deserializer with a second impedance mismatch. At least one of the serializer and deserializer includes an equalizer that attenuates a frequency component of the signal at half of the symbol rate relative to a frequency component of the signal at one third of the symbol rate. Though such attenuation may reduce signal-to-noise ratio, an improved communications performance may nevertheless be achieved by suppression of signal reflections.

Serdes equalization for short, reflective channels

Decision feedback equalizers and equalization methods may employ fractional tap unrolling and/or probability-based decision threshold placement. One illustrative fractional tap unrolling equalization method embodiment includes: tracking preceding symbol decisions; converting an equalized signal into tentative symbol decisions with a precompensation unit; and selecting from the tentative symbol decisions based on the preceding symbol decisions. The precompensation unit has a decision element for each combination of a first number of speculative preceding symbols, with comparators in each decision element using a first type of symbol decision threshold that accounts for trailing intersymbol interference from the corresponding combination, and with an additional comparator in at least one of the decision elements using a second type of symbol decision threshold that accounts for trailing intersymbol interference from a second number of speculative preceding symbols, the second number being greater than the first.

Decision feedback equalizer with fractional tap unrolling

Multi-function level finder for serdes

An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop that provides a clock signal; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal; a timing error estimator that produces a timing error signal; a first feedback path coupling the timing error signal to the phase interpolator to minimize a phase component of the estimated timing error; a second feedback path coupling the timing error signal to the phase interpolator; and a third feedback path coupling the timing error signal to the fractional-N phase lock loop, the second and third feedback paths minimizing a frequency offset component of the estimated timing error.

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Fremont, CA, United States of America

Junqing (Phil) Sun