International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Adeia Semiconductor Bonding Technologies Inc.

Adeia Semiconductor Solutions LLC

Junli Wang

Kangguo Cheng

Veeraraghavan S Basker

Theodorus E Standaert

Brent A Anderson

Ruilong Xie

Hong He

Chih-Chao Yang

Lawrence Alfred Clevenger

Juntao Li

Dechao Guo

Ruqiang Bao

Alexander Reznicek

Bruce Bennett Doris

Fee Li Lie

Heng Wu

Shogo Mochizuki

Terence B Hook

Huiming Bu

Baozhen Li

Kirk David Peterson

Nicolas J Loubet

Chen Zhang

Hemanth Jagannathan

Albert Manhee Chu

Tenko Yamashita

Carl John Radens

Balasubramanian Pranatharthiharan

Xuefeng Liu

Lan Yu

Su Chen Fan

Stuart A Sieg

Julien Frougier

Yann Mignot

Terry Allen Spooner

Albert M Young

Chun-chen Yeh

John H Zhang

Joshua M Rubin

Chun-Chen Yeh

Keith Kwong Hon Wong

Christopher J Penny

Yunpeng Yin

Yongan Xu

Stefan Schmitz

Ali Khakifirooz

Hsueh-Chung Chen

Effendi Leobandung

Sivananda K Kanakasabapathy

John Edward Sheets, Ii

Sanjay C Mehta

Hosadurga K Shobha

Kisik Choi

Gauri V Karve

Chiahsun Tseng

Edward J Nowak

Choonghyun Lee

Chi-Chun Liu

Steven J Bentley

Michael P Belyansky

Joe Lee

Siyuranga O Koswatta

Peng Xu

Xin Miao

Jingyun Zhang

Reinaldo Ariel Vega

Kern Rim

Hiroaki Niimi

Ravikumar Ramachandran

Marc Adam Bergendahl

John Ryan Sporre

Nicholas Anthony Lanzillo

Huai Huang

Somnath Ghosh

Devendra K Sadana

Takashi Ando

David V Horak

Vijay Narayanan

Judson Robert Holt

Qing Liu

Zuoguang Liu

Robert Russell Robison

Min Gyu Sung

Andrew Mark Greene

Pranita Kerber

Indira P Seshadri

Christopher Joseph Waskiewicz

Kwan-Yong Lim

Timothy James McArdle

Jeffrey C Shearer

Chanro Park

Oleg Gluschenkov

Mukta G Farooq

Zhenxing Bi

Koichi Motoyama

Muthumanickam Sankarapandian

Anthony I Chou

Rishikesh Krishnan

Gen Tsutsui

Pietro Montanini

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a stack of transistors with a first transistor on top of a second transistor, where a gate of the first transistor has a first width; a gate of the second transistor has a second width; and the first width is narrower than the second width, and where the first and the second transistor respectively have a first gate extension at a first side of the stack and a second gate extension at a second side of the stack, the first gate extension at the first side of the stack being narrower than the second gate extension at the second side of the stack, with the first side being opposite the second side. A method of manufacturing the semiconductor structure is also provided.

Asymmetric gate extension in stacked FET

An approach forming semiconductor structure composed of one or more stacked semiconductor devices that include at least a top semiconductor device, a bottom semiconductor device under the top semiconductor, and contacts to each of the semiconductor devices. The approach provides a stacked semiconductor structure where the bottom semiconductor device is wider than the top semiconductor device. The approach also provides the stacked semiconductor structure where the width of the top semiconductor device is the same as the width of the bottom semiconductor device. The approach includes forming a contact to a side of the bottom semiconductor device when the width of the top semiconductor device is the same as the bottom semiconductor device. The approach includes forming a contact to epitaxy grown on a portion of the top and a side of the bottom semiconductor device when the bottom semiconductor device is larger than the top semiconductor device.

Bottom contact with self-aligned spacer for stacked semiconductor devices

Embodiments herein describe semiconductor devices with single diffusion breaks that are narrower than the gates of transistors in those devices. That is, rather than forming the diffusion breaks using a dummy gate (which would result in the diffusion breaks having the same width as the gates of the transistors) the embodiments herein use different means to establish the width of the diffusion break. As a result, the diffusion break can be narrower than traditional diffusion breaks formed using dummy gates, thereby saving area in the semiconductor device.

Narrowing single diffusion break

A semiconductor structure including a vertical semiconductor channel region, a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region, a metal gate disposed around the vertical semiconductor channel region, where a first portion of the metal gate extends above the vertical semiconductor channel region, and a gate contact entirely above the vertical semiconductor channel region.

Vertical transistor with reduced cell height

A semiconductor device includes a substrate; a set of first transistors positioned on an upper surface of the substrate, each of the set of first transistors comprising a first gate and a first dielectric; an insulating layer positioned on an upper surface of the set of first transistors; and a set of second transistors positioned over the set of first transistors and with the set of first transistors on an upper surface of the insulating layer, each of the set of second transistors having a second gate and a second dielectric; wherein each of the first dielectrics is connected to a sidewall of each of a corresponding first gate; and wherein each of the second dielectrics is connected to the insulating layer.

Multi-VT solution for replacement metal gate bonded stacked FET

A microelectronic structure including a plurality of lower transistors and a plurality of upper transistor, where each of the plurality of lower transistors and the plurality of upper transistors includes a plurality of channel. Where an upper center vertical axis of each of the plurality of upper transistors is staggered from a lower center vertical axis of each of the lower transistors. A lower gate cut is located between each of the plurality of lower transistors. A first upper gate cut located adjacent to a first upper transistor of the plurality of upper transistors, where the first upper gate cut is in direct contact with a plurality of first channels of the first upper transistor.

Method and structure of forming independent contact for staggered CFET

A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions. The semiconductor device also includes a gate cut region at cell boundaries between the first and second S/D epitaxial regions, a dielectric liner and a dielectric core formed in the gate cut region, and a backside power rail (BPR) and a backside power distribution network (BSPDN). The semiconductor device also includes a power via passing through the dielectric core and connecting to the BPR and BSPDN, first metal contacts formed in contact with the first and second S/D epitaxial regions, and a via to backside power rail (VBPR) contact. The dielectric liner separates the power via from the first S/D epitaxial region.

Semiconductor device with power via

A semiconductor device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer of the semiconductor device includes a standard-gate field-effect transistor. The second semiconductor layer of the semiconductor device includes an extended-gate field-effect transistor. The first semiconductor layer and the second semiconductor layer are formed on top of one another.

Stacked FETS including devices with thick gate oxide

A semiconductor structure is presented including a first source/drain (S/D) epi region having a first contact completely wrapping around the first S/D epi region, the first contact electrically connected to a backside power delivery network (BSPDN) and a second S/D epi region having a second contact directly contacting a first sidewall, a second sidewall, and a top surface of the second S/D epi region, the second contact electrically connected to back-end-of-line (BEOL) components.

Full wrap around backside contact

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a static random access memory (SRAM) cell. The SRAM cell may include a first section of the SRAM cell with a first pull-up transistor, first pull-down transistor, and first pass-gate transistor. The SRAM cell may include a second section of the SRAM cell with a second pull-up transistor, second pull-down transistor, and second pass-gate transistor. The first section of the SRAM cell and the second section of the SRAM cell may be arranged in a non-rectangular cell layout with the first pass-gate located at a first end of the non-rectangular cell layout and the second pass-gate at a second end of the non-rectangular cell layout opposite the first end.

High density stacked vertical transistor static random access memory structure

FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

FinFET devices

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Bulk nanosheet with dielectric isolation

A semiconductor device includes a FinFET fin. The same FinFET fin is associated with a bottom FinFET and a top FinFET. The FinFET fin includes a lower channel portion, associated with the bottom FinFET, a top channel portion, associated with the top FinFET, and a channel isolator between the bottom channel portion and the top channel portion. A lower gate includes a vertical portion that is upon a sidewall of the bottom channel portion. An isolation layer may be formed upon the lower gate if it is desired for the top FinFET fin and the bottom FinFET fin to not share a gate. An upper gate is upon the top channel portion and is further upon the isolation layer, if present, or is upon the lower gate.

Upper and lower gate configurations of monolithic stacked FinFET transistors

A semiconductor structure including a first logic cell having a first plurality of nanosheet devices along an axis and a second logic cell having a second plurality of nanosheet devices along the axis. Nanosheets of the second plurality of nanosheet devices are wider than nanosheets of the first plurality of nanosheet devices. The first logic cell is a same type as the second logic cell. The first and second logic cells can include inverter circuits or NAND circuits or NOR circuits. When the first logic cell has a height X, a width Y, and an effective width (W) Z, then the second logic cell has a height 2X, a width Y, and W>2.5 Z.

Staggered stacked circuits with increased effective width

Embodiments of present invention provide a semiconductor device. The semiconductor device includes a silicon (Si) substrate containing a set of short channel field-effect-transistors (FETs); a germanium (Ge) layer on top of the Si substrate containing a set of long channel p-type FETs (PFETs); and an oxide semiconductor layer on top of the Ge layer containing a set of long channel n-type FETs (NFETs), wherein the set of short channel FETs, long channel PFETs, and long channel NFETs are interconnected through a set of far-back-end-of-line (FBEOL) layers.

Vertically integrated semiconductor device

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Slingerlands, NY, United States of America

Junli Wang