Samsung Electronics Co., Ltd.

Lg Cns Co., Ltd.

Junkyu Yang

Phil Ouk Nam

Dongchul Yoo

Kihyun Hwang

Woong Hee Lee

JinGyun Kim

Jaeyoung Ahn

Woosung Lee

Daehong Eom

Woonkyung Lee

Hanmei Choi

Jaegoo Lee

Chanjin Park

HongSuk Kim

Byong-Hyun Jang

Tae-Jong Han

Chaeho Kim

Gyungjin Min

Daewoong Kim

Juhyung Kim

Yoochul Kong

Woojin Jang

Youngseon Son

Byong-hyun Jang

Kwangyoung Lee

A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

Semiconductor memory devices and methods of fabricating the same

A semiconductor device includes word lines vertically stacked on top of each other on a substrate, insulating patterns between the word lines, a vertical pillar connected to the substrate, and residual sacrificial patterns on the substrate at sides of the word lines. The vertical pillar penetrates the word lines and the insulating patterns. Each of the insulating patterns includes a first portion between the word lines and a second portion extending from the first portion and between the residual sacrificial patterns. A first thickness of the first portion is smaller than a second thickness of the second portion.

Semiconductor device having a vertical pillar connected to the substrate

A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

Three-dimensional semiconductor memory device and method for fabricating the same

Three-dimensional semiconductor memory device

A mobile bill providing server receives bill details for a particular user from a mobile bill issuing server and provides a mobile bill to a mobile terminal available for installation of a bill viewer, the mobile bill being dependent upon the bill viewer. A mobile bill providing method includes searching for the mobile terminal associated with the particular user and determining whether the bill viewer has been installed in the mobile terminal. If the bill viewer has not been installed in the mobile terminal, the method includes transmitting an electronic bill independent of the bill viewer and guidance information for installation of the bill viewer to the mobile terminal, waiting for a period of time until the bill viewer is installed in the mobile terminal, and when the bill viewer is installed, transmitting the mobile bill to the mobile terminal.

Method of providing mobile bill and server for performing the same

Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

Three dimensional semiconductor memory device and method of manufacturing the same

Provided are semiconductor devices and methods of forming the same. A device isolation structure in the semiconductor device includes a gap region. A dielectric constant of a vacuum or an air in the gap region is smaller than a dielectric constant of an oxide layer and, as a result coupling and attendant interference between adjacent cells may be reduced.

Semiconductor devices including device isolation structures and method of forming the same

A three-dimensional (3D) nonvolatile memory device includes a vertical stack of nonvolatile memory cells on a substrate having a region of first conductivity type therein. A dopant region of second conductivity type is provided in the substrate. This dopant region forms a P-N rectifying junction with the region of first conductivity type and has a concave upper surface that is recessed relative to an upper surface of the substrate upon which the vertical stack of nonvolatile memory cells extends. An electrically insulating electrode separating pattern is provided, which extends through the vertical stack of nonvolatile memory cells and into the recess in the dopant region of second conductivity type.

Three-dimensional semiconductor memory devices and methods for manufacturing same

Growing community of inventors

Seoul, South Korea

Junkyu Yang