Hitachi, Ltd.

Hitachi Device Engineering Co., Ltd.

Junko Nakase

Takashi Nakamoto

Hirotsugu Kojima

Nobukazu Doi

Yukio Fujii

Katsumi Matsuno

Hiroshi Gunji

Norio Sumi

There is provided a filtering circuit whose circuit scale is small and which is suitable for a digital data string in which data of luminance signals Y and color-difference signals Cb and Cr are regularly inserted or multiplexed. The digital filtering circuit comprises a delay line composed of a plurality of D flip-flops which is operative with frequency of the data string in which the luminance signals Y and the color-difference signals Cb and Cr are regularly inserted or multiplexed a plurality of multipliers for multiplying a plurality of taps of the delay line by respective coefficients and an adder for adding outputs of said multipliers, wherein the taps connected to the multipliers is switched by selectors. It allows one digital filtering circuit to be used for processing the signals Y, Cb and Cr in a time division manner to realize the digital filtering circuit which uses less multipliers and adders and whose circuit scale is small.

Digital filtering circuit

There is provided a filtering circuit whose circuit scale is small and which is suitable for a digital data string in which data of luminance signals Y and color-difference signals Cb and Cr are regularly inserted or multiplexed. The digital filtering circuit includes a delay line composed of a plurality of D flip-flops which is operative with frequency of the data string in which the luminance signals Y and the color-difference signals Cb and Cr are regularly inserted or multiplexed a plurality of multipliers for multiplying a plurality of taps of the delay line by respective coefficients and an adder for adding outputs of said multipliers, wherein the taps connected to the multipliers is switched by selectors. It allows one digital filtering circuit to be used for processing the signals Y, Cb and Cr in a time division manner to realize the digital filtering circuit which uses less multipliers and adders and whose circuit scale is small.

A data demultiplexer includes a write controller, a memory, an analyzing processing unit, and transfer control units. The write controller writes packets which have arrived thereat into the memory in the order of arrival and sends the write information to the analyzing processing unit. The analyzing processing unit analyzes packets in the order of arrival on the basis of the write information and sends only the result of analysis to the transfer control units. On the basis of the result of analysis, the transfer control units send data read from the memory in the order of packet arrival to the decoder. A data demultiplexer capable of reducing the processing in the analyzing processing unit can be provided.

Data demultiplexer

An error correcting system for performing error correction for error codewords received sequentially in a codeword string on a pipeline processing basis. The system comprises a processing block for generating syndrome data on the basis of parity symbols of each of the codewords, a processing block for performing logical processing operation to derive error locations and error values on the basis of the syndrome data, and a processing block for performing correcting operation for delayed codewords based on the error locations and values. These three processing blocks start their processing operation when receiving individual control signals based on reset signals indicative of leading heads of the respective codewords in the string and delayed by mutually different delay times. With regard to incomplete ones of the codewords that are shorter than a right correct codeword length, the logical processing operation for the error location and error evaluation as well as the error correcting operation is inhibited.

Error correcting system

The present invention features performance of operation processing between a signal obtained by converting a coefficient into a Booth code with a Booth encoder, storing the Booth code in a memory device in advance and reading out the stored Booth code for processing an input signal in a semiconductor operation device or a digital filter. As a result, a coding operation by a Booth encoder of the present invention will be performed only once at the time of rewriting a coefficient and will not be repeated, thereby enabling a high-speed operation and realizing reduction of circuit scale at the same time by using an encoded Booth code directly in an operation after a coefficient has been determined.

Semiconductor operation device with memory for storing operation codes

When each sample is expressed by digital signals of 8 bits, 8 bits constituting each of the digital signals are divided into data of upper 5 bits including the most significant bit, and data of lower 4 bits including the least significant bit. These two data are respectively inputted to two filter circuit units, and are simultaneously subjected to a filtering process separately. Outputs of these two filter circuit units are inputted to an adder. In the adder, the output of the filter circuit unit being data of upper 5 bits subjected to a filtering process is weighted by a factor of 2 to the 4th power, and the weighted output is added to the output of the other filter circuit unit. The results of adding are outputted from the adder as signals obtained by the original digital signals of 8 bits subjected to the filtering process. Since the number of bits of individual data is made small by the division, the operation speed of computing elements and the number of times of recursive or multiple uses of computing elements are increased so that the circuit scale of the entire filter circuit can be reduced.

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Kodaira, Japan

Junko Nakase