Nec Corporation

Junko Morikawa

Hidemasa Takahashi

Hiroshi Yamashita

Hiroshi Nozue

Kazunori Asano

Fumiaki Katano

It is an object of the invention to solve a problem that a gate breakdown voltage and RF characteristics of a field effect transistor, which is provided with a double recess composed of a wide recess and a narrow recess, is not satisfactory. This problem results from the fact that a AlGaAs layer is exposed on a surface of the wide recess. The method for fabricating the field effect transistor comprise the steps of successively forming the first active layer, the first stopper layer, the second active layer, the second stopper layer and the third active layer on a substrate, forming a wide recess by etching a predetermined part of the third active layer till the second stopper is exposed, exposing the second active layer by removing the second stopper layer exposed on the bottom surface of the wide recess, and forming a narrow recess, which has a smaller aperture area than that of the wide recess, by etching a predetermined part of the exposed second active layer till the first stopper layer is exposed.

Method for manufacturing a field effect transistor

A field effect transistor has a preselected build up resistance with respect to an I-V characteristic of the transistor. In this event, a first GaAs layer is formed on a GaAs substrate. Further, an AlGaAs layer is formed on the first GaAs layer and has a predetermined impurity concentration and a preselected Al composition ratio. Moreover, a gate electrode is placed on the AlGaAs layer to form a schottky contact with the AlGaAs layer. In addition, a second GaAs layers are arranged on both sides of the gate electrode via a recess and are formed on said AlGaAs layer. Finally, source and drain electrodes are formed on the second GaAs layers. With such a structure, the Al composition ratio is determined within a preselected range defined by a relationship between the impurity concentration and the build up resistance.

Field effect transistor and method of manufacturing the same

A field effect transistor includes (a) a semi-insulating GaAs substrate, (b) a step-doped structured active layer including an n type GaAs layer deposited on the substrate, and an n type GaAs layer or a non-doped GaAs layer deposited on the n type GaAs layer, the n type GaAs layer or non-doped GaAs layer being formed with at least one recess, and (c) a gate electrode formed in the recess so that the gate electrode is oriented in such a direction that drain current runs in the active layer along crystal orientation &lsqb;01(&minus;1)&rsqb;. The field effect transistor enhances linearity of transfer conductance, and further improves strain characteristic.

Field effect transistor and method of fabricating the same

Field effect transistor and a method for manufacturing a same

A comb-shape MESFET assembly has a plurality of unit FETs including first, second and third groups of unit FETs. The pinch-off voltages of the unit FETs are different from group to group by a step difference. The different pinch-off voltages provide a tailored change in the third-order intermodulation distortion in the output of the MESFET assembly. The step difference in the pinch-off voltage is generated by different thicknesses or impurity concentrations of a semiconductor active layer, different gate length of the unit FETs or different types of stress in the gate insulator films.

Method of forming a metal-semiconductor field effect transistors having

A comb-shape MESFET assembly has a plurality of unit FETs including first, second and third groups of unit FETs. The pinch-off voltages of the unit FETs are different from group to group by a step difference. The different pinch-off voltages provide a tailored change in the third-order intermodulation distortion in the output of the MESFET assembly. The step differences in the pinch-off voltage is generated by different thicknesses or impurity concentrations of a semiconductor active layer, different gate length of the unit FETs or different types of stress in the gate insulator films.

Metal semiconductor field effect transistors having improved

The field effect transistor includes (a) a plurality of drain finger electrodes, source finger electrodes and gate finger electrodes disposed in an active region on a semiconductor substrate so that each of the gate finger electrodes is sandwiched between each of the drain and source finger electrodes, (b) a source electrode pad for electrically connecting the source finger electrodes to each other, and (c) a gate electrode pad for electrically connecting the gate finger electrodes to each other, the gate electrode pad being disposed farther away from the active region than the source electrode pad. By disposing the gate electrode pad farther away from the active region than the source electrode pad, it is possible to arrange the source electrode pads at higher density, which is accompanied by a lesser number of source finger electrodes associated with each of the source electrode pads. Thus, it is possible to decrease source inductance, and avoid parasitic oscillation.

Field effect transistor including a plurality of electrode units

A method for writing on a semiconductor wafer using electron beams is provided. One embodiment of the method includes the steps of using electron beams to irradiate a semiconductor substrate on which a resist layer has been formed, to thereby draw patterns on the resist layer, and then baking the resist layer and substrate in a vacuum.

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Tokyo, Japan

Junko Morikawa