Fujitsu Corporation

Junko Kumagai

Hideaki Konishi

Hitoshi Watanabe

Takahisa Hiraide

Daisuke Maruyama

Ryuji Shimizu

Koichi Itaya

Hitoshi Yamanaka

Kazuyuki Yamamura

Toshihito Shimizu

Osamu Ōkano

Yuko Katoh

Naoko Karasawa

Takeshi Doi

Daisuke Tsukuda

A design support apparatus includes a unit that inputs a user net list created by using hard macro cells excluding test circuits, and a unit that arranges hard macro cells using a frame into which hard macro cells, where timing-converged physical information includes test terminals, and test circuits are embedded as arrangement/wiring information. Moreover, includes a unit that arranges and wires the test circuits using the arrangement/wiring information of the test circuit embedded into the frame, a unit that recognizes arrangement/wiring information where the arrangement/wiring information of the test circuits is removed from arrangement/wiring information obtained by wiring, and a unit outputs a net list of a logic structure.

Method and apparatus for supporting designing of LSI, and computer product

An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

Testing apparatus and testing method for an integrated circuit, and integrated circuit

Growing community of inventors

Kawasaki, Japan

Junko Kumagai