Renesas Electronics Corporation

Sanyo Electric Co., Ltd.

Sanyo Semiconductor Manufacturing Co., Ltd.

Junko Kimura

Takao Hidaka

Mikihiko Komatsu

Hirohiko Hayakawa

Yoshitaka Muramoto

Toshiyuki Imai

Ryosuke Enomoto

Toshitaka Ukai

Akiko Fukute

A semiconductor device is provided for measuring a voltage of each of plural unit cells series-coupled in multi-stage and configuring an assembled battery. The semiconductor device includes two terminals coupled to two nodes which are electrodes of a unit cell and coupled with other unit cells, and a voltage measurement circuit which measures the inter-terminal voltage between the two terminals. The device also includes a down-convert level shifter circuit which converts the inter-terminal voltage into a low-potential-side inter-terminal voltage based on a ground potential, and a comparator circuit which compares the converted low-potential-side inter-terminal voltage with a predetermined reference voltage. The semiconductor device further includes an up-convert level shifter circuit which converts a low-potential-side shunt control signal based on the ground potential into a high-potential-side shunt control signal, and a switch which short-circuits the two terminals via a resistor based on the converted high-potential-side shunt control signal.

Semiconductor device and battery voltage monitoring device

In battery voltage monitoring ICs for measuring voltages of unit cells of an assembled battery, communication with a system control unit is realized in consideration of fail-safe. The system control unit and the battery voltage monitoring ICs are coupled to each other by a communication path using a daisy chain. Each battery voltage monitoring IC has a placement setting pin designating, by a binary code, a unit cell group to which the IC is coupled, in the unit cell groups. When it is detected that the Hamming distance between the code indicative of coupling to a group of the highest potential or a group of the lowest potential and a state actually set in the placement setting pin is 1, some failure such as line disconnection, short-circuit, or the like in the placement setting pins is detected, and the communication path is interrupted.

A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.

Semiconductor device for battery power voltage control

A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires respectively. In another example, fourth and fifth pad are disposed along a side different form a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.

A first switch circuit includes first and second N-type MOSFETs. A second switch circuit includes third and fourth N-type MOSFETs. A control signal is input to a first inverter and a third inverter, the output of the first inverter input to a second inverter and the gate of the fourth MOSFET, the output of the second inverter input to the gate of the first MOSFET, the output of the third inverter input to a fourth inverter and the gate of the third MOSFET, the output of the fourth inverter input to the gate of the second MOSFET. A first input voltage is connected to the source of the second MOSFET and the sources of N-type MOSFETS in the third and fourth inverters. A second input voltage is connected the source of the fourth MOSFET and the sources of N-type MOSFETS in the first and second inverters.

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Tokyo, Japan

Junko Kimura