Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kaisha

Other

Renesas Electronics Corporation

Mitsubishi Denki Kabushiki Kaihsa

Junko Izumitani

Takashi Yamashita

Yoshifumi Takata

Noriaki Fujiki

Shigeru Harada

Hiroki Takewaka

Atsushi Ishii

Kazuyoshi Maekawa

Nobuyoshi Hattori

Noboru Morimoto

Yoko Miyazaki

Masahiko Ikeno

Yasutaka Nishioka

Takao Kamoshima

Shoichi Fukui

Shigeki Sunada

To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.

Semiconductor device, and manufacturing method thereof

A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse.

Semiconductor device including fuse elements and bonding pad

A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, depositing by plasma chemical vapor deposition a second insulating film covering the bonding pad and the fuse elements, the second insulating film having planar portions between the fuse elements and ridged portions opposite the fuse elements, depositing by plasma chemical vapor deposition a third insulating film covering the second insulating film, etching the third insulating film to form a first hole exposing a first region of the second insulating film, opposite the fuse elements, and a second hole exposing a second region of the second insulating film, opposite at least part of said bonding pad, and etching the second insulating film to form a third hole exposing at least part of the bonding pad.

Method of manufacturing semiconductor device including bonding pad and fuse elements

The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer formed from one selected from precious metals and alloys containing the precious metals as main components.

Semiconductor device having a multilayer wiring structure and pad electrodes protected from corrosion, and method for fabricating the same

A semiconductor device has a multilayer interconnection structure in which a plurality of interconnection layers is formed in an insulating film. The multilayer interconnection structure has a first metal film made of a first material and functioning as a first interconnection belonging to an interconnection layer other than an uppermost interconnection layer, a second metal film made of a second material and functioning as a second interconnection belonging to the uppermost interconnection layer, a third metal film made of the first material and belonging to an interconnection layer other than the uppermost interconnection layer and functioning as a bonding pad, an opening formed in the insulating film and having its bottom defined by the third metal film, and a bonding wire connected to the third metal film through the opening. The second material has a lower resistance and is more susceptible to oxidation than the first material.

Semiconductor device with internal bonding pad

Method of manufacturing semiconductor device and semiconductor device

A dielectric layer for capacitive element is formed on a lower electrode. An interlayer insulating layer is formed on the lower electrode and the dielectric layer for capacitive element. A plug hole reaching the dielectric layer for capacitive element is formed in the interlayer insulating layer. Upper electrodes are formed to fill in the plug hole and positioned opposite to the lower electrode with the dielectric layer for capacitive element interposed. The dielectric layer for capacitive element is in contact with the upper surface of the lower electrode at a region directly below the plug hole and a region outside the sidewall of the plug hole. Thus, a semiconductor device having a capacitive element with a greater capacitance which prevents diffusion of metal atoms from the lower electrode as well as a manufacturing method thereof are provided.

Manufacturing method of semiconductor device having capacitive element

An interconnection forming step provides an interconnection with an improved yield, a low cost and a high reliability. A semiconductor device includes an insulating layer formed on a silicon substrate and having a groove extending in a predetermined direction. A distance between side walls defining insulating layer increases as a position moves away from silicon substrate. The semiconductor device includes a conductive layer filling groove.

Semiconductor device and method of manufacturing the same

The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer. formed from one selected from precious metals and alloys containing the precious metals as main components.

Semiconductor device having a multilayer wiring structure and pad electrodes protected from corrosion and method for fabricating the same

Disclosed is an apparatus for manufacturing a semiconductor device including a metal film which is formed on a semiconductor substrate in a film formation region containing the interior of a hole formed in the semiconductor substrate. The apparatus includes a degassing chamber, a film forming chamber, and a cooing chamber. The degassing chamber,is provided for carrying out a degassing process by heating the semiconductor substrate to a degassing temperature. The film forming chamber,is provided for forming a metal film on the film formation region in a state in which the semiconductor substrate is heated to a film formation temperature. The cooling chamber,is provided for cooling, after completion of the degassing process and before beginning of the formation of the metal film, the semiconductor substrate to a cold temperature being lower than the film formation temperature and in a range of &minus;50&deg; C. to 150&deg; C.

Semiconductor device and apparatus and method for manufacturing the same

An ordinary user can easily learn a step at which a problem occurs during semiconductor manufacturing processes and improve the yield of manufacturing products and the quality of the products. At a certain in-line inspection step, a CPU (3) stores data signals (V1) taken by an inspection apparatus (1) into a memory (2), and reads a result (V6) obtained at a precedent step and stores the same in the memory (2). The CPU (3) reads stored data signals (V2) from the memory (2), performs comparison or referral on data about defects which are detected at a current step and the result (V6) regarding the precedent step, and generates a defect data analysis processing result signal (V5) regarding the current step. The result (V5) consists of disappeared defect data, common defect data, new defect data to which a label of a current step number is assigned, and reappeared defect data. The CPU (3) performs the processing above for each in-line inspection step, edits resultant data, and generates histogram data which provide the number of detected defects and the number of disappeared defects for each step.

Growing community of inventors

Tokyo, Japan

Junko Izumitani