International Business Machines Corporation

Samsung Electronics Co., Ltd.

Junka Okazawa

Kohji Hosokawa

Masatoshi Ishii

Takeo Yasuda

Yutaka Nakamura

Atsuya Okazaki

Takayuki Osogami

Masahiro Murakami

Masahiro Hori

Norio Fujita

Akiyo Iwashina

A synapse memory system includes a plurality of synapse memory cells, a write portion, and read drivers. Each synapse memory cells is disposed at cross points of axon lines and dendrite lines and includes a plurality of analog memory devices and each synapse memory cell is configured to store a weight value according to an output level of a write signal. The plurality of analog memory devices is combined to constitute each synapse memory cell. The write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell and the output controller is configured to control the output level of the write signal of the write driver. The read drivers are configured to read the weight value stored in the synapse memory cells.

Performance and area efficient synapse memory cell structure

A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.

Neuromorphic chip for updating precise synaptic weight values

A spiking neural network device including a spiking neural network circuit including a crossbar array of plural synapses; plural axons connected with the spiking neural network circuit, the plural axons receiving input of a spike signal; and plural Poisson spike generators respectively provided for the plural axons. Each Poisson spike generator can be set whether or not to emit the spike signal based on an input signal to be processed, and each Poisson spike generator can, be set to emit the spike signal being configured to generate a Poisson spike train different from each other. and supply the Poisson spike train to a corresponding one of the plural axons.

On-chip Poisson spike generation

A neuromorphic synapse array is provided which ensures that a neuron model as such McCulloch-Pitts is dependent on nonlinearity with a single polarity weight cell. The neuromorphic synapse array includes a plurality of synaptic array cells, a plurality of operation column arrays, and a reference column array. The synaptic array cells respectively have a single polarity synapse weight and are classified into operation synapse cells and reference synapse cells for shifting a product-sum of the operation synapse cells. The operation column arrays are defined by the operation synapse cells aligned in column of the array. The reference column array is defined by the reference synapse cells aligned in column of the array.

Weight shifting for neuromorphic synapse array

A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.

Monitoring potential of neuron circuits

Methods and systems are provided for operating a neuromorphic system for generating neuron and synapse activities. The method includes: preparing at least one digital timer in the neuromorphic system, each of the at least one digital timers including multi-bit digital values; generating time signals using the at least one digital timer; emulating an analog waveform of a neuron spike; updating parameters of the neuromorphic system using the time signals and the current values of the parameters; presetting, using a processor, the digital values of the at least one digital timer to initial values when the spike input is provided to the node; and updating, using the processor, the digital values of the at least one digital timer with a specified amount when there is an absence of a spike input to the node.

Timing sequence for digital STDP synapse and LIF neuron-based neuromorphic system

A method and system are provided for updating synapse weight values in neuromorphic system with Spike Time Dependent Plasticity model. The method includes selectively performing, by a hardware-based synapse weight incrementer or decrementer, one of a synapse weight increment function or decrement function, each using a respective lookup table, to generate updated synapse weight values responsive to spike timing data. The method further includes storing the updated synapse weight values in a memory. The method additionally includes performing, by a hardware-based processor, a learning process to integrate the updated synapse weight values stored in the memory into the Spike Time Dependent Plasticity model neuromorphic system for improved neuromorphic simulation.

LUT based synapse weight update scheme in STDP neuromorphic systems

Described is a neuromorphic system implemented in hardware that implements neuron membrane potential update based on the leaky integrate and fire (LIF) model. The system further models synapse weights update based on the spike time-dependent plasticity (STDP) model. The system includes an artificial neural network in which the update scheme of neuron membrane potential and synapse weight are effectively defined and implemented.

Digitial STDP synapse and LIF neuron-based neuromorphic system

A method and system are provided for updating a neuron membrane potential in a spike time dependent plasticity model in a Neuromorphic system. The method includes approximating a shape of an analog spike signal from an axon input using a hardware-based digital axon timer. The method further includes generating a first intermediately updated neuron membrane potential value from a current axon timer value, a current synapse weight value and a current neuron membrane potential value using a first look-up table and an accumulator. The method also includes generating a second intermediately updated neuron membrane potential value with a leak decay effect using a second look-up table and the first intermediately updated neuron membrane potential value. The method additionally includes generating a final updated neuron membrane potential value based on a comparison of the second intermediately updated neuron membrane potential value with a neuron fire threshold level using a comparator.

LUT based neuron membrane potential update scheme in STDP neuromorphic systems

Digital STDP synapse and LIF neuron-based neuromorphic system

A computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other, wherein the memory subsystem comprises a memory controller connected to the system bus, the computer system includes an up/down counter for counting a number of access requests and a number of requests other than access requests, a comparator for comparing the count of the up/down counter with a predetermined threshold value stored in a register, and a clock gate circuit for generating clock gate signals to decimate an operating clock of the memory controller in response to the comparison result of the comparator.

Memory subsystem and computer system

A method including estimating an access request frequency from a CPU to a memory subsystem by counting a number of CPU access requests and a number of requests other than CPU access requests, wherein the CPU is connected to the memory subsystem via a system bus, and the memory subsystem includes a memory controller connected to the system bus, and a DDR memory, including the estimated access request frequency with a predetermined threshold value stored in a register, generating a clock gate signal to decimate an operating clock of the memory controller in response to a result of comparing the estimated access request frequency with the predetermined threshold value, generating a dummy cycle signal to delay the timing of signal data output from the memory controller to the system bus, and generating a clock enable signal to decimate an operating clock of the DDR memory.

The present invention provides a computer system including a CPU with an L2 cache, a bus master device and a bus slave device. They are connected via a system bus to communicate with each other. The computer systemincludes: a transaction monitorfor monitoring first transaction states TrC-TrCn between a CPUand an L2 cache, and second transaction states from TrBto TrBn between a system busand the L2 cache, between the system busand a bus master deviceor between the system busand bus slave devices; and a clock generatorable to change the frequency FreqC-FreqSof the clock of the CPU, the system bus, and the bus slave devicesaccording to the first transaction and second transaction states received from the transaction monitor

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Kyoto, Japan

Junka Okazawa