International Business Machines Corporation

Globalfoundries Inc.

Elpis Technologies Inc.

Junjun Li

Robert J Gauthier, Jr

Tenko Yamashita

Theodorus E Standaert

Souvick Mitra

Huiming Bu

Christopher Stephen Putnam

Michel J Abou-Khalil

Tom C Lee

Robert Russell Robison

Shidong Li

Hongqing Zhang

Zhigang Song

Guoda Lian

Anthony K Stamper

Jeffrey Bowman Johnson

Kiran V Chatty

Jay A Bunt

Hongmei Li

Robert Gauthier

John B Campi

Mujahid Muhamad

A flexible circuit substrate that includes a conductive line on a flexible substrate and at least one slot in the conductive line on the flex substrate, where at one slot is in an area of the flexible circuit substrate that will be bent to prevent an open in the conductive line on the flexible substrate.

Flexible circuit structure for circuit line bending

Tamper-respondent assemblies are provided which include a circuit board, an enclosure assembly mounted to the circuit board, and a pressure sensor. The circuit board includes an electronic component, and the enclosure assembly is coupled to the circuit board to enclose the electronic component within a secure volume. The enclosure assembly includes an enclosure with a sealed inner compartment, and a structural material within the sealed inner compartment of the enclosure. The structural material within the enclosure inhibits deflection of the enclosure due to a pressure differential between pressure of the sealed inner compartment and pressure around, at least in part, the enclosure. The pressure sensor senses pressure within the sealed inner compartment of the enclosure to facilitate identifying a pressure change indicative of a tamper event.

Tamper-respondent assembly with structural material within sealed inner compartment

Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an cathode on a substrate and a anode on the substrate. The anode is in electrical contact with the cathode. The method further includes forming a device between the cathode and the anode. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Structures, methods and applications for electrical pulse anneal processes

Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.

Electrostatic discharge devices and methods of manufacture

Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both.

Multi-gate field effect transistor (FET) including isolated FIN body

Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.

Metal-insulator-metal capacitors with high capacitance density

Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.

Device structures compatible with fin-type field-effect transistor technologies

Semiconductor structures providing protection against electrostatic events of both polarities are provided. A pair of p-n junctions is provided underneath a shallow trench isolation portion between a first-conductivity-type well and each of a signal-side second-conductivity-type well and an electrical-ground-side second-conductivity-type well in a semiconductor substrate. A second-conductivity-type doped region and a first-conductivity-type doped region are formed above each second-conductivity-type well such that a portion of the second-conductivity-type well resistively separates the second-conductivity-type doped region and the first-conductivity-type doped region within the semiconductor substrate. Each of the second-conductivity-type doped regions is wired either to a signal node or electrical ground. One of the two npn transistors and one of the two p-n diodes, each inherently present in the semiconductor structure, turn on to provide protection against electrical discharge events involving either type of excessive electrical charges.

Bidirectional electrostatic discharge protection structure for high voltage applications

Electrostatic discharge (ESD) protection device and process for protecting a conventional FET. The device includes at least one FET body forming a resistance, and a triggering circuit coupled to a protection FET and the resistance. The resistance raises a voltage of the at least one body, such that the protection FET is triggered at a voltage lower than the conventional FET.

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Cupertino, CA, United States of America

Junjun Li