Renesas Electronics Corporation

Mitsubishi Denki Kabushiki Kaisha

Matsushita Electric Industrial Co., Ltd.

Renesas Technology Corp.

Junjiro Sakai

Hirokazu Sayama

Fumihiko Hayashi

Kouichirou Tsujita

Akira Imai

Takahiro Mori

Takeo Ishibashi

Teruhiko Kumada

Hideharu Nobutoki

Susumu Matsumoto

Akemi Moniwa

Koichiro Narimatsu

Satoshi Iida

Toshiyuki Toyoshima

Atsumi Yamaguchi

Makoto Koshimizu

Michinari Yamanaka

Yasutaka Nishioka

Akihiro Nakae

Kouji Oda

Yoshiharu Ono

Ayumi Minamide

Shingo Tomohisa

Manabu Ishibashi

Fumio Iwamoto

Yuki Murayama

There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench reaching the semiconductor substrate is formed within the semiconductor layer. The first insulating film is formed on the inner side surface of the first trench such that a portion of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected with the semiconductor substrate and formed on the inner side surface of the first trench through the first insulating film. In plan view, a first length of the first trench in an extending direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extending direction, and equal to or less than 30 &#x3bc;m.

A mask having mask patterns for the transfer of a desired circuit pattern, a method for manufacturing the mask, and a semiconductor device manufacturing method using the mask, are provided. There are extracted two rectangular aperture patterns which are adjacent each other in an obliquely disposed state with respect to an X axis in an XY plane. The thus-extracted two rectangular aperture patterns are rotated at a certain angle so that a pattern edge corresponding to one side of one of the rectangular aperture patterns and a pattern edge corresponding to one side of the other rectangular aperture pattern are opposed in parallel to each other. The two rectangular aperture patterns thus rotated at a certain angle are then subjected to optical proximity effect correction to form two corrected rectangular aperture patterns.

Mask, method for manufacturing the same, and method for manufacturing semiconductor device

A photomask is disclosed which can suppress deterioration of the depth of focus even in the case where main features are arranged randomly. Sub-features are replaced by a quadrangular sub-feature located inside an external quadrangle which includes as part of its outer periphery the outermost portions of the original sub-features. The sub-feature after the replacement is preferably in a square shape and the length of one side thereof is determined in accordance with the length of the associated external quadrangle. A central position of the sub-feature after the replacement is preferably coincident with the center of the external quadrangle or the center of gravity of the region which includes the original sub-features.

Photomask, apparatus for manufacturing semiconductor device having the photomask, and method of manufacturing semiconductor device using the photomask

A via-filling material includes a polymer containing a repeating unit represented bywherein Rone of hydrogen, fluorine, chlorine, bromine, and methyl group; Ris one of hydrogen, a Calkyl group, and a Calkyl group in which the hydrogen is replaced by at least one of fluorine, chlorine, and bromine; and X is &#x2014;C(&#x2550;O)O&#x2014; or &#x2014;S(&#x2550;O)O&#x2014;. This via-filling material does not generate deposits around an opening of a via hole during plasma etching and provides a semiconductor integrated circuit with high reliability, even when a trench wider than the via hole is formed by plasma etching around the via hole filled with the via-filling material.

Via-filling material and process for fabricating semiconductor integrated circuit using the material

It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole () reaching an etching stopper film () is formed, annealing is carried out at 300 to 400&#xb0; C. with the via hole () opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring () which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate. Consequently, a by-product staying in an interface of an upper protective film () and an interlayer dielectric film () having a low dielectric constant and a by-product staying in an interface of the etching stopper film () and the interlayer dielectric film () having a low dielectric constant are discharged so that an amount of the residual by-product can be decreased.

Electronic device manufacturing method

An antireflection coating has two-layer structure including lower and upper silicon nitride films (p-SiN films) formed by plasma CVD. For the lower p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.9 nor more than 2.5, the imaginary part is set in the range of not less than 0.9 nor more than 1.7, and the film thickness is set in the range of not less than 20 nm nor more than 60 nm. For the upper p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.7 nor more than 2.4, the imaginary part is set in the range of not less than 0.15 nor more than 0.75, and the film thickness is set in the range of not less than 10 nm nor more than 40 nm.

Antireflection coating and semiconductor device manufacturing method

A pattern determination method includes a step for setting an interconnection width and the like, a step for representing the mask pattern and aperture configuration in functions, steps for calculating amplitude distribution of exposure light, a step for calculating intensity distribution of exposure light at an image plane, steps for calculating maximum, minimum, and reference intensity of exposure light, a step for determining exposure margin and focus margin, a step for storing data of qualification/disqualification of optical image formation, and a step for providing a display of a table. A configuration including four openings is set for the aperture. Determination of whether an optical image of an interconnection pattern can be formed or not is facilitated by the table in setting the interconnection pattern of a semiconductor device.

Pattern determination method

Growing community of inventors

Tokyo, Japan

Junjiro Sakai