Qualcomm Incorporated

International Business Machines Corporation

Globalfoundries Inc.

Other

Globalfoundries U.S. 2 LLC

Junjing Bao

Naftali Eliahu Lustig

Samuel S Choi

Andrew Herbert Simon

Ronald G Filippi

Griselda Bonilla

Ye Lu

John Jianhong Zhu

Haining S Yang

Giridhar Nallapati

Bin Yang

Stanley Seungchul Song

Xia Li

Jeffrey Xu

Choh Fei Yeap

Peijie Feng

Wai-Kin Li

Thomas W Dyer

Stephen Edward Greco

Kaushik Chanda

James A Culp

Stephan Grunow

Mustafa Badaroglu

Dan Moy

Vladimir Machkaoutsan

Matthew S Angyal

Chenjie Tang

Niladri Mojumder

Da Yang

Lixin Ge

Yun Yue

Daniel C Edelstein

Seung Hyuk Kang

Elbert Emin Huang

Matthew Michael Nowak

Yanxiang Liu

Yu Lu

Tien-Jen Cheng

Haitao Cheng

Yan Zun Li

Xuesong Li

Kwanyong Lim

Shaoning Yao

Hyunwoo Park

Samuel S S Choi

Ming-Huei Lin

Youseok Suh

Jie Deng

Wai-kin Li

Lawrence Alfred Clevenger

Ping-Chuan Wang

Kern Rim

Richard Stephan Wise

Xiao Hu Liu

Vincent James McGahay

Erdem Kaltalioglu

Yiheng Xu

Periannan Chidambaram

Gengming Tao

Jun Yuan

Yunsheng Song

Andrew Tae Kim

Lijuan Zhang

Chao Song

Joyeeta Nag

Yongchun Xin

Yangyang Sun

Jang Sim

Jun Chen

Jihong Choi

Zhigang Song

ChihWei Kuo

Chih-Sung Yang

Jeffrey Junhao Xu

Niladri Narayan Mojumder

Valdimir Machkaoutsan

Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a gate structure disposed on a substrate, a gate spacer adjacent to the gate structure, a source/drain structure adjacent to the gate spacer, a first dielectric layer disposed on the substrate and the source/drain structure, an etch stop spacer over the first dielectric layer and adjacent to the gate spacer, and an etch stop layer over the gate structure, the gate spacer, and the etch stop spacer. The semiconductor structure further includes a source/drain contact extending through the etch stop layer and the first dielectric layer and in contact with the source/drain structure, a sidewall of the source/drain contact adjoining a sidewall of the etch stop layer and a sidewall of the etch stop spacer.

Self-aligned source/drain contact structure and method of manufacturing the same

Disclosed are devices that include a contact for electrical connection with a source/drain. The contact occupies a full width of a contact well other than areas occupied by sidewall spacers. As a result, high resistivity (due to the presence of liners and nucleation layers within the contact well in conventional devices) is reduced or eliminated.

Selective contact on source and drain

Disclosed are complementary field effect transistors (CFETs) with balanced n and p drive current, and methods for making the same. In an aspect, a CFET structure comprises an nFET with horizontal p-doped nanosheet channels arranged in a first vertical stack, each horizontal p-doped nanosheet channel having a width W, and connecting a first source contact to a first drain contact through a first gate-all-around (GAA) region having a length L. The CFET structure further comprises a pFET with horizontal n-doped nanosheet channels arranged in a second vertical stack disposed on the first vertical stack, each horizontal n-doped nanosheet channel having a width W, and connecting a second source contact to a second drain contact through a second GAA region having a length L, wherein W/Lis not equal to W/L

Complementary field effect transistor (CFET) with balanced N and P drive current

Disclosed are apparatuses including a transistor cell and methods of fabricating the transistor cell. The transistor cell may include a substrate, an active region and a gate having a gate contact in the active region. The transistor cell may further include a first portion of a spacer of the gate contact formed from a first material, and a second portion of the spacer of the gate contact formed from a second material.

Transistor cell with self-aligned gate contact

A metal oxide metal (MOM) capacitor and methods for fabricating the same are disclosed. The MOM capacitor includes a first metal layer having a first plurality of fingers, each of the first plurality of fingers configured to have alternating polarities. A high resistance (Hi-R) conductor layer is disposed adjacent the first metal layer in a plane parallel to the first metal layer.

Back-end-of-line (BEOL) high resistance (Hi-R) conductor layer in a metal oxide metal (MOM) capacitor

Three-dimensional (3D) interconnect structures employing via layer conductive structures in via layers are disclosed. The via layer conductive structures in a signal path in an interconnect structure are disposed in respective via layers adjacent to metal lines in metal layers. The via layer conductive structures increase the conductive cross-sections of signal paths between devices in an integrated circuit (IC) or to/from an external contact. The via layer conductive structures provide one or both of supplementing the height dimensions of metal lines and electrically coupling metal lines in the same or different metal layers to increase the conductive cross-section of a signal path. The increased conductive cross-section reduces current-resistance (IR) drop of signals and increases signal speed. As metal track pitches are reduced in size, signal path resistance increases. The via layer conductive structures are provided to reduce or avoid an even greater increase in resistance in the signal paths.

Three-dimensional (3D) interconnect structures employing via layer conductive structures in via layers and related fabrication methods

Integrated circuits (ICs), including capacitors and inductors, employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related fabrication methods. By directly coupled, it is meant that there is not an intermediate vertical interconnect access (via) layer with a via(s) interconnecting the metal lines in vertically-adjacent interconnect layers. An overlying and underlying metal line in respective and vertically-adjacent overlying and underlying interconnect layers are directly coupled to each other without the need for an intermediate via layer. For example, directly coupled metal in adjacent interconnect layers of IC can reduce contact resistance between the metal lines and reduce the overall height of the IC. An insulating layer(s) can be disposed in select recessed regions between the overlying interconnect layer and the underlying interconnect layer to insulate an overlying metal line from another vertically-intersecting underlying metal line that are not intended to be electrically coupled together.

Integrated circuits (ICs) employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related methods

In an aspect, a semiconductor device includes a gate. The gate includes a first portion that is located on one end of the gate, a second portion that is located on an opposite end of the gate from the first portion, and a third portion that is located in-between the first portion and the second portion. A first cap located on top of the first portion. A second cap located on top of the second portion. The third portion is capless. A gate contact is located on top of the third portion.

Gate contact isolation in a semiconductor

In some aspects, a semiconductor die includes an insulation layer disposed on a substrate, a gate spacer disposed in the insulation layer, a gate disposed between the gate spacer, a first dielectric gate layer disposed on the gate between the gate spacer, a second dielectric gate layer disposed on the first dielectric gate layer between the gate spacer, a gate contact coupled to the gate and in contact with the first dielectric gate layer and the second dielectric gate layer, and a source/drain contact that has a single inner spacer.

Semiconductor having a source/drain contact with a single inner spacer

A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage.

Multi-gate high electron mobility transistors (HEMTs) employing tuned recess depth gates for improved device linearity

Disclosed are semiconductor devices including a double gate metal oxide semiconductor (MOS) transistor and methods for fabricating the same. The double gate MOS transistor includes a first back gate, a second back gate, and a first dielectric layer disposed on the first back gate and on the second back gate. An MX2 material layer is disposed on the first dielectric layer, a second dielectric layer disposed on the MX2 material layer, and a work function metal (WFM) is disposed on the second dielectric layer. A front gate is disposed on the WFM, which fills a space between the first back gate and the second back.

Three dimensional (3D) double gate semiconductor

An integrated device that includes a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, where the first plurality of channels is located between the first source and the first drain; at least one inner spacer located between two adjacent channels from the first plurality of channels; at least two voids located between the two adjacent channels; and a first gate surrounding the first plurality of channels.

Field effect transistor (FET) comprising inner spacers and voids between channels

Disclosed are standard cells and methods for fabricating standard cells used in semiconductor device design and fabrication. Aspects disclosed include a standard cell having a plurality of wide metal lines. The wide metal lines being formed from copper. The standard cell also includes a plurality of narrow metal lines. The narrow metal lines are formed from a material that has a lower resistance than copper for line widths on the order of twelve nanometers or less.

Hybrid low resistance metal lines

Disclosed are optimized contract structures and fabrication techniques thereof. At least one aspect includes a semiconductor die. The semiconductor die includes a substrate and a contact disposed within the substrate. The contact includes a first portion with a first vertical cross-section having a first cross-sectional area. The first vertical cross-section has a first width and a first height. The contact also includes a second portion with a second vertical cross-section having a second cross-sectional area less than the first cross-sectional area. The second vertical cross-section includes a lower portion having the first width and a second height less than the first height, and an upper portion disposed above the lower portion and having a second width less than the first width and having a third height less than the first height.

Optimized contact structure

Certain aspects of the present disclosure relate to a semiconductor device (e.g., a gate-all-around (GAA) semiconductor device) comprising at least one superlattice fin. One example superlattice fin includes a first plurality of nanosheets composed of a first semiconductor material and a second plurality of nanosheets composed of a second semiconductor material, the second semiconductor material being different from the first semiconductor material, wherein a width of a first nanosheet in the first plurality of nanosheets differs from a width of a second nanosheet in the second plurality of nanosheets, the second nanosheet being adjacent to the first nanosheet.

Semiconductor device with superlattice fin

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San Diego, CA, United States of America

Junjing Bao