Samsung Electronics Co., Ltd.

Postech Academy-industry Foundation

Junjin Kong

Hong Rak Son

Changkyu Seol

Eun Chu Oh

Jaehong Kim

Kijun Lee

Seonghyeog Choi

Yong June Kim

Pilsang Yoon

Younggeon Yoo

Hyejeong So

Dong-Min Shin

Kyoung Lae Cho

Myungkyu Lee

Sunghye Cho

Heeseok Eun

Kyeongcheol Yang

Donghwan Lee

Seung-Hwan Song

Jinman Han

Hong-Rak Son

Eunae Lee

Young-Seop Shim

Geunyeong Yu

Yeonggeol Song

Amit Berman

Tae-Hwan Kim

Heewon Lee

Dongmin Shin

Sae-Young Chung

Yesin Ryu

KyoungLae Cho

Han Woong Yoo

JongHa Kim

Sejin Lim

Jiyoup Kim

Yong-June Kim

Donggi Lee

Jihyun Choi

Kwanghoon Kim

Daewook Kim

Dongsup Jin

Seung-Chan Lim

Mankeun Seo

Youngsuk Ra

Namshik Kim

Jungsoo Chung

Biwoong Chung

Yongjune Kim

Euncheol Kim

Seonghoon Woo

Youngjun Hwang

Bohwan Jun

Beom Kyu Shin

Chanho Yoon

Beomkyu Shin

Seungkyung Ro

Seongnam Kwon

Uri Beitler

Seongsik Hwang

Sunggi Ahn

Bumseok Yu

Hee Chang Cho

Amir Bennatan

Amitai Perlstein

Soonjae Won

Yongtaew Yim

Wootae Chang

Lanying Zhao

Sungik Choi

Jongha Kim

Dongsoo Jun

Hyunseuk Yoo

A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.

Memory device performing refresh operation and method of operating the same

An error correction device includes a low density parity check (LDPC) decoder and an adaptive decoding controller. The LDPC decoder iteratively performs LDPC decoding on data by using a decoding parameter. The adaptive decoding controller calculates an error rate depending on a result of the LDPC decoding and adjusts the decoding parameter depending on the error rate.

Error correction device, operating method of error correction device, and controller including error correction device

A method of operating a memory controller that performs decoding by using a parity check matrix corresponding to a convolution-type low density parity check (LDPC) code includes receiving a codeword from at least one memory device, the codeword including a first sub-codeword and a second sub-codeword; decoding a first sub-codeword into first data by using first sliding windows in a first direction, set based on a first sub-matrix included in the parity check matrix and associated with the first sub-codeword; and decoding a second sub-codeword into second data by using second sliding windows in a second direction, set based on a second sub-matrix included in the parity check matrix and associated with the second sub-codeword.

Method of operating memory controller for performing encoding and decoding by using a convolution-type low density parity check code

A solid-state drive (SSD) may include a volatile buffer such as DRAM, a non-volatile memory (NVM) such as NAND Flash connected to the volatile buffer, and a capacitor connected to both, where the capacitor may have an energy capacity insufficient to supply the buffer and NVM using a normal supply voltage in a normal mode, but sufficient to supply the buffer and NVM using at least one reduced supply voltage in a temporary mode; and a related method may include programming data to the NVM by temporarily reducing the supply voltage to the NVM, and writing data to the NVM using the reduced supply voltage.

Low-power data transfer from buffer to flash memory

A storage device is provided as follows. A nonvolatile memory device includes blocks, each block having sub-blocks erased independently. A memory controller performs a garbage collection operation on the nonvolatile memory device by selecting a garbage collection victim sub-block among the sub-blocks and erasing the selected garbage collection victim sub-block to generate a free sub-block. The memory controller selects the garbage collection victim sub-block using valid page information of each sub-block and valid page information of memory cells adjacent to each sub-block.

Storage device including nonvolatile memory device and garbage collection method thereof

A method of decoding may include performing fewer than number of sensing operations of multilevel cells within a nonvolatile memory device, decoding pages corresponding to each of the sensing operations while correcting a channel error using an RIO code, and extracting user data from the decoded pages.

Data coding to reduce read-sensing operations in storage device

A low-density parity check (LDPC) decoder may include a variable node processing unit and a check node processing unit. The check node processing unit includes memory elements storing a check node value. The memory elements are interconnected through two or more paths, and each of the paths may include a total or partial cyclic permutation of the memory elements to transmit the check node value.

Low-density parity check decoder, a storage device including the same, and a method

A method for controlling a nonvolatile memory device includes requesting a plurality of first sampling values from the nonvolatile memory device, each of the first sampling values representing the number of memory cells having a threshold voltage between a first sampling read voltage and a second sampling read voltage. The first sampling values are processed through a non-linear filtering operation to estimate the number of memory cells having the threshold voltage between the first sampling read voltage and the second sampling read voltage.

Memory system using non-linear filtering scheme and read method thereof

A redundant array of inexpensive disks (RAID) controller of a RAID storage system that includes one or more storage devices includes an error correction code (ECC) result manager configured to manage information of ECC result indicators when a data chunk that includes one or more ECC data units having an uncorrectable ECC error is read from among a plurality of data chunks dispersively stored in the one or more storage devices, each of the plurality of data chunks including a plurality of ECC data units, the ECC result indicators respectively indicating whether the plurality of ECC data units included in the plurality of data chunks has an uncorrectable ECC error; and an uncorrectable error counter configured to calculate a number of ECC result indicators indicating an uncorrectable ECC error among ECC result indicators corresponding to ECC data units having a same order in each of the plurality of data chunks.

RAID controller device and storage device configured to recover data having uncorrectable ECC error

A storage device is provided which includes an ECC circuit. At a write operation, the ECC circuit generates a CRC (cyclic redundancy check) parity corresponding to data and generates an ECC (error correction code) parity corresponding to the data using an error correction code. At a read operation about the data stored in the at least one nonvolatile memory device, the ECC circuit corrects an error of the data using the CRC parity and the ECC parity.

Memory controller, storage device including the same and data encoding and decoding methods thereof

A storage device may include a nonvolatile memory device, a buffer memory, and a controller. The controller may perform first accesses on the nonvolatile memory device using the buffer memory, collect access result information and access environment information of the first accesses in the buffer memory, and generate an access classifier that predicts a result of a second access to the nonvolatile memory device by performing machine learning based on the access result information and the access environment information collected in the buffer memory.

Storage devices including nonvolatile memory devices and access methods for nonvolatile memory devices

The inventive concepts relate to an operation method of an error correction decoder correcting an error of data read from a nonvolatile memory. The operation method may include receiving the data from the nonvolatile memory, performing a first error correction with respect to the received data in a simplified mode, and performing, when the first error correction fails in the simplified mode, a second error correction with respect to the received data in a full mode. When the first error correction of the simplified mode is performed, a part of operations of the second error correction of the full mode may be omitted.

Error correction decoder and operation method of the error correction decoder

A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a row decoder circuit connected to the memory cell array through a plurality of word lines; and a page buffer circuit connected to the memory cell array through bit lines. The row decoder circuit applies read voltages to a selected word line during a read operation. During a read operation performed with respect to each of N logical pages (N being a positive integer) of memory cells connected to the selected word line, the row decoder circuit applies a read voltage from among adjacent N read voltages to the selected word line without applying read voltages other than the adjacent N read voltages to the selected word line. The adjacent N read voltages include a second highest read voltage among the read voltages.

Nonvolatile memory device and operating method of nonvolatile memory device

Growing community of inventors

Yongin-si, South Korea

Junjin Kong