Kneron (taiwan) Co., Ltd.

Junjie Su

Chun-Chen Liu

Bike Xie

Jie Wu

Hsiang-Tsun Li

Bodong Zhang

Yuan Du

Yi-Chou Chen

Yunhan Ma

Mingzhe Jiang

After inputting input data to a floating pre-trained convolution neural network to generate floating feature maps for each layer of the floating pre-trained CNN model, a statistical analysis on the floating feature maps is performed to generate a dynamic quantization range for each layer of the floating pre-trained CNN model. Based on the obtained quantization range for each layer, the proposed quantization methodologies quantize the floating pre-trained CNN model to generate the scalar factor of each layer and the fractional bit-width of a quantized CNN model. It enables the inference engine performs low-precision fixed-point arithmetic operations to generate a fixed-point inferred CNN model.

Low precision and coarse-to-fine dynamic fixed-point quantization design in convolution neural network

A system for operating a floating-to-fixed arithmetic framework includes a floating-to-fix arithmetic framework on an arithmetic operating hardware such as a central processing unit (CPU) for computing a floating pre-trained convolution neural network (CNN) model to a dynamic fixed-point CNN model. The dynamic fixed-point CNN model is capable of implementing a high performance convolution neural network (CNN) on a resource limited embedded system such as mobile phone or video cameras.

Deep neural network with low-precision dynamic fixed-point in reconfigurable hardware design

A method of pruning a batch normalization layer from a pre-trained deep neural network model is proposed. The pre-trained deep neural network model is inputted as a candidate model. The candidate model is pruned by removing the at least one batch normalization layer from the candidate model to form a pruned candidate model only when the at least one batch normalization layer is connected to and adjacent to a corresponding linear operation layer. The corresponding linear operation layer may be at least one of a convolution layer, a dense layer, a depthwise convolution layer, and a group convolution layer. Weights of the corresponding linear operation layer are adjusted to compensate for the removal of the at least one batch normalization. The pruned candidate model is then output and utilized for inference.

Lossless model compression by batch normalization layer pruning in deep neural networks

A method of compressing a pre-trained deep neural network model includes inputting the pre-trained deep neural network model as a candidate model. The candidate model is compressed by increasing sparsity of the candidate, removing at least one batch normalization layer present in the candidate model, and quantizing all remaining weights into fixed-point representation to form a compressed model. Accuracy of the compressed model is then determined utilizing an end-user training and validation data set. Compression of the candidate model is repeated when the accuracy improves. Hyper parameters for compressing the candidate model are adjusted, then compression of the candidate model is repeated when the accuracy declines. The compressed model is output for inference utilization when the accuracy meets or exceeds the end-user performance metric and target.

Self-tuning incremental model compression solution in deep neural network with guaranteed accuracy performance

A memory cell includes a first charge trap transistor and a second charge trap transistor. The first charge trap transistor has a substrate, a first terminal coupled to a first bitline, a second terminal coupled to a signal line, a control terminal coupled to a wordline, and a dielectric layer formed between the substrate of the first charge trap transistor and the control terminal of the first charge trap transistor. The second charge trap transistor has a substrate, a first terminal coupled to the signal line, a second terminal coupled to a second bitline, a control terminal coupled to the wordline, and a dielectric layer between the substrate of the second charge trap transistor and the control terminal of the second charge trap transistor. Charges are either trapped to or detrapped from the dielectric layer of the first charge trap transistor when writing data to the memory cell.

Memory cell with charge trap transistors and method thereof capable of storing data by trapping or detrapping charges

An image processing system includes an image capturing device, a pixel binning device, a temporal filter, a first memory, a re-mosaic device, a second memory, and a blending device. The image capturing device is used for capturing a raw image. The pixel binning device is coupled to the image capturing device for outputting an enhanced image according to the raw image. The temporal filter is coupled to the pixel binning device for outputting a preview image according to the enhanced image. The first memory is used for buffering the raw image. The re-mosaic device is coupled to the first memory for outputting a processed image. The second memory is used for buffering the enhanced image. The blending device is coupled to the re-mosaic device and the second memory for outputting a snapshot image according to the processed image and the enhanced image.

Growing community of inventors

San Diego, CA, United States of America

Junjie Su