Taiwan Semiconductor Manufacturing Comp. Ltd.

Cadence Design Systems, Inc.

Mentor Graphics Corporation

Junjiang Lei

Danping Peng

Weiping Fang

Srini Doddi

Le Hong

Frank E Gennari

Ya-Chieh Lai

Matthew W Moskewicz

Daniel Beylkin

Sagar Vinodbhai Trivedi

Fangbo Xu

Srinivas Rao Doddi

Kenji Yamazoe

Kenneth Lik Kin Ho

Zhiru Yu

Kuanghao Lay

Kuang-Hao Lay

Yuan Fang

Lin Ping Zhang

Yuansheng Ma

George P Lippincott

Weinong Lai

Georg P Lippincott

Mei-Fang Shen

Kenneth L Ho

YiNing Pan

Methods of semiconductor device fabrication are provided. In an embodiment, a method of semiconductor device fabrication includes receiving a first mask design comprising a first mask function, determining a transmission cross coefficient (TCC) of an exposure tool, decomposing the TCC into a plurality orders of eigenvalues and a plurality orders of eigenfunctions, calculating a kernel based on the plurality orders of eigenvalues and the plurality orders of eigenfunctions; and determining a first sub-resolution assist feature (SRAF) seed map by convoluting the first mask function and the kernel.

Sub-resolution assist features

A system and a method of optimizing an optical proximity correction (OPC) model for a mask pattern of a photo mask is disclosed. A machine learning (ML) based model builder includes an OPC model, measurement data and a random term generator. Random terms are generated in a M-dimensional space by the random term generator. The ML based model builder classifies the random terms to clusters by applying a classifying rule. A representative subset of the random terms is determined among the classified clusters, and the representative subset is added to the OPC model.

Machine learning based model builder and its applications for pattern transferring in semiconductor manufacturing

Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Synchronized parallel tile computation for large area lithography simulation

A method of making a mask includes computing a mask volume correction matrix for a given mask layout to be used to perform a lithography process. The mask volume correction matrix represents a diffraction field for a predetermined thickness of a material of the mask. A simulated mask pattern is computed by applying the mask volume correction matrix to the given mask layout. The simulated mask pattern is provided to a mask making tool.

Lithographic mask correction using volume correction techniques

Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type features. An initial guiding pattern characterized by a plurality of guiding pattern parameters is constructed for two or more via-type features in a layout design based on target values of location and size parameters for the two or more via-type features. Predicted values of the location and size parameters are then extracted from the initial guiding pattern based on simulations or correlation information between the plurality of guiding pattern parameters and the location and size parameters. Based on the predicted values of the location and size parameters, the target values of location and size parameters and the correlation information, a modified guiding pattern is determined by adjusting one or more parameters of the plurality of guiding pattern parameters. The extraction and determination operations may be iterated.

Guiding patterns optimization for directed self-assembly

Aspects of the disclosed technology relate to techniques of optical proximity correction for directed self-assembly guiding patterns. An initial mask pattern for photomask fabrication is first generated by performing a plurality of conventional optical proximity correction iterations. Predicted print errors for two or more via-type features are then determined based on a predicted guiding pattern for the two or more via-type features, a target guiding pattern for the two or more via-type features, and correlation information between a plurality of guiding pattern parameters and location and size parameters for the two or more via-type features. Here the predicted guiding pattern is derived based on the initial mask pattern. Based on the predicted print errors and the correlation information, the initial mask pattern is adjusted to generate a new mask pattern.

Optical proximity correction for directed-self-assembly guiding patterns

Aspects of the invention relate to techniques for applying edge fragment correlation information to optical proximity correction. Neighbor-aware edge adjustment values for the edge fragments are computed based on edge placement error values and edge fragment correlation information. The computation comprises: selecting a group of edge fragments around a center edge fragment, calculating preliminary neighbor-aware edge adjustment values based on the edge placement error values and the edge fragment correlation information for the group of edge fragments, storing the preliminary neighbor-aware edge fragment adjustment value for the center edge fragment, and repeating the selecting, the calculating and the storing with each of the edge fragments being the center edge fragment. The computed neighbor-aware edge adjustment values are combined with conventional edge adjustment values and the edge fragments are adjusted accordingly. The process may be repeated for a number of times.

Neighbor-aware edge fragment adjustment for optical proximity correction

Aspects of the invention relate to techniques for applying edge fragment correlation information to optical proximity correction. Conventional edge adjustment values for the edge fragments are first derived from edge placement error values. Neighbor-aware edge adjustment values for the edge fragments are then computed based on the edge placement error values, the conventional edge adjustment values and edge fragment correlation information. The computation comprises: calculating pseudo edge placement error values by subtracting neighboring edge movement contribution values from the edge placement error values and calculating the neighbor-aware edge adjustment values based on the pseudo edge placement error values. The computed neighbor-aware edge adjustment values are combined with conventional edge adjustment values and the edge fragments are adjusted accordingly. The process may be repeated for a number of times.

Optical proximity correction based on edge fragment correlation

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Bellevue, WA, United States of America

Junjiang Lei