Sharp Kabushiki Kaisha Corporation

Matsushita Electric Industrial Co., Ltd.

Junji Tanaka

Yukihisa Orisaka

Toshio Watanabe

Yoshiki Sano

Yutaka Nakamura

Yukio Nishikawa

Kenji Hirano

Yukihiko Ueno

Hiroyuki Shigematsu

Katsunori Takeda

Hiroshi Nishida

Kiyohisa Matsui

Hiroshi Nakao

Masaaki Kurata

Masamitsu Takahashi

Kozo Kitamura

Masanobu Watanabe

Hiroo Katsura

Makoto Kado

Takayoshi Sasaoka

Kentaro Hama

Eiji Tanaka

Hirofumi Yanaru

Kiyoshi Kakuda

Fumihiro Inoue

Toshiyuki Nakai

Kouichi Tsubouchi

Yusuke Suzuoki

Yoshifumi Morimoto

Tsutomu Takahara

A combination terminal unit includes at least: inputting device for inputting a retrieval item and an option item; line connecting means capable of establishing a line connection to any of a plurality of media; storage device for storing therein a plurality of retrieval information entities; display device for displaying any of the retrieval information entities; and retrieval controller for, if a retrieval item is inputted by the inputting device, reading out retrieval information entities relevant to the retrieval item from the storage device and displaying the information entities thus read out on the display device and, if a particular retrieval information entity is selected from the displayed retrieval information entities by the inputting device, actuating the line connecting means to establish a line connection to a location of the particular retrieval information entity.

Combination terminal unit

A data transfer apparatus utilizing infrared rays characterized in that one transmission unit of transmission data formed by combining digital data comprising a bit row represented by two values '0' and '1' into a predetermined format is stored in a transmission buffer, transmission suspension time that should be added after the transmission of the one transmission unit of transmission data from an array of adjacent bit values that constitute the one transmission unit of transmission data is determined, and one transmission unit of transmission data is sent at an interval of the above transmission suspension time.

Data transfer apparatus utilizing infrared rays

A wireless signaling system includes a plurality of transmitters and a single receiver. The transmitter sequentially transmits serial data blocks to the receiver. Each data block includes a transmitter identification code and predetermined time intervals defining the beginning and end of the data block. The receiver receives the data block, detects the time intervals before and after the received data block to recognize reception of a complete data block, and checks the transmitter identification code included in the received data block to identify the transmitter.

Wireless signaling system

An integrated circuit may have a mode to be switched over if a predetermined signal voltage is input through a mode switching terminal when the predetermined voltage is applied to one or more signal input terminals. The integrated circuit is provided with a voltage setting circuit disposed between the signal input terminal and the logic circuit, for setting the signal input terminal to receive any voltage in the range of a ground voltage to a power source voltage in response to a signal voltage input through the mode switching terminal.

Integrated circuit with voltage setting circuit

A differential amplifier includes a noninverting input transistor including a gate for receiving a first input signal; and an inverting input transistor including a gate for receiving a second input signal. A difference between the first input signal and the second input signal is amplified. The noninverting input transistor and the inverting input transistor are each formed of a depletion MOSFET.

Differential amplifier

A sample and hold circuit is arranged to have a first shift register, a second shift register, a first group of sample and hold elements, a second group of sample and hold elements, and a phase switching circuit. The first shift register has a serial-in and parallel-out function and serves to shift an input sampling pulse in synchronization to the first shift clock. The second shift register has a serial-in and parallel-out function and serves to shift the input sampling pulse in a synchronous to a second shift clock being different from the first shift clock by a predetermined angle of phase. The first group of sample and hold elements serves to sample an analog signal in synchronization to an output from the first shift register. The second group of sample and hold elements serves to sample an analog signal in synchronization an output from the second shift register. The phase switching circuit serves to switch a phase relation between the first shift clock and the second shift clock in a manner so as to keep a predetermined phase angle between the first and the second shift clocks.

Sample and hold circuit being arranged for easily changing phases of

Disclosed is a sample-and-hold circuit. A plurality of input signals are applied to the capacitors through the corresponding analog switches. The capacitors are charged to the instantaneous voltages of input signals when the corresponding analog switches are conducting. An output circuit comprising a plurality of input circuit legs and an output is provided. Each input circuit leg includes series connected input transistor and switching transistor. Input circuit legs are connected in parallel. A plurality of inputs of the switching trainsistors are supplied with input switching signals to turn on the switching transistors in a systematic chosen sequence. And a plurality of inputs of the input transisntrs are connected to the capacitors to put the voltage across one of the capacitors to the output during the time when the corresponding analog switch is in the hold mode and the corresponding switch transisor is conducting.

Sample-and-hold circuit

A sample/hold apparatus includes at least one sample/hold circuit. The at least one sample/hold circuit has a resistor connected to an input bus at one end thereof, a sampling gate connected to the other end of the resistor at one end thereof for opening and closing in response to a sampling signal supplied thereto, and a first capacitor connected to the other end of the sampling gate at one end thereof for holding analog data supplied from the input bus through the resistor and the sampling gate.

Apparatus for sampling and holding analog data for a liquid crystal

A data input system useful in a data base such as an address data management system. This data input system can reduce the number of key operation and the possibility of erroneously inputting data. This system comprises: a display for displaying input data; a first memory for storing data displayed on the display, a second memory for temporarily storing the displayed data; and a control unit for displaying the data stored in the second memory.

Data input system with automatic duplication of repetitive data to a

An integrated circuit having a predetermined function includes a signal generating circuit for generating a signal for performing a reliability test predetermined in the integrated circuit, a detecting circuit for outputting a signal which indicates a detection at a time when a rise of a supply voltage to the integrated circuit is detected, and a control circuit for controlling the integrated circuit so that a predetermined reliability test of the integrated circuit is performed by using the signal output from the signal generating circuit in case that a predetermined selection signal is applied to an input terminal of the control circuit in response to the signal output from the detecting circuit at a time of a rise of the supply voltage.

Integrated circuit capable of testing reliability

An output circuit having a buffer, the buffer including the first transistor which receives at a gate thereof a periodic input voltage and the second transistor, the first and the second transistors being connected in series across a power line and a ground line, a junction of the first and second transistors being connected to an output terminal. The output circuit includes a circuit for applying, to a gate of the second transistor, a first voltage for the second transistor to serve as a bias transistor for charging a load connected to the output terminal with a voltage corresponding to the input voltage, and the second voltage greater than the first voltage for the second transistor to serve as a discharge transistor for discharging the load.

Output circuit with buffer

A data processing apparatus includes a key input device, a display device, a schedule data memory for storing schedule data attached with a data and a time within the date inputted from the key input device by the day, a time calculator for calculating a present date and time based on a date and time initially set, an alarm setting device for setting a requisition of alarm in a schedule data of a desired data and time included in the schedule data stored in the schedule data memory, a comparator for comparing the present date and time outputted from the time calculator with the date and time attached to the schedule data set with the requisition of the alarm by the alarm setting device and a display controller for simultaneously displaying the schedule data set with the requisition of the alarm and other schedule data being adjacent to said schedule data when the result of the comparison by the comparator is conformable.

Data processing apparatus with schedule creation, prioritization,

An analog signal extracting circuit includes a sampling gate for sampling an analog input voltage, a differential amplifier for receiving the output of the sampling gate, and a buffer for buffering the output of the differential amplifier. The differential amplifier has a p-channel MOS transistor serving as an input transistor. The sampling gate applies a voltage to a gate of the p-channel MOS transistor. The buffer has a source follower type n-channel MOS transistor. The differential amplifier applies its output to a gate of the n-channel MOS transistor.

Analog signal extracting circuit

A piezoelectric transducer arranged to allow the adjustment of its oscillation frequency. The piezoelectric transducer comprises a piezoelectric member which is encased in an airtight housing having at least one portion which allows transmission of light. The piezoelectric member has on its surfaces electrodes and is coupled to one end portions of electrical conductors the other end portions of which extend toward the external of said airtight housing. Also housed in the airtight housing is a deposition member which is evaporated in response to illumination of a light beam. The deposition member is provided so as to face the light-transmitting portion of the airtight housing.

Piezoelectric transducer and method of adjusting oscillation frequency

By forming corner parts of transparent quartz plates and the glass plate in rounded arc shape, in a mirror-surface finishing to accurate plane, polishing powder grain can flow out smoothly and evenly from all the periphery of the plates, and thus the surfaces of those component plates are finished to accurate plate of mirror-surfaces, without making a recessed part at their central parts which has been observed in the conventional plates of rectangular form, and hence, a quartz optical filter made by laminating the improved plates having accurate planes attains an excellent performance characteristic which does not give any degradation in light propagation.

Growing community of inventors

Sakurai, Japan

Junji Tanaka