Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Junji Takiguchi

Kazuyoshi Nishi

Osamu Sarai

Tetsuo Asada

Tooru Suyama

Kazuhito Ito

A driving circuit for a display device for selectively outputting a driving voltage positive or negative with respect to a given reference voltage of the display device in accordance with an image signal, includes an input stage circuit; and an output stage circuit for outputting a driving voltage between a given high voltage and a first intermediate voltage or a driving voltage between a second intermediate voltage and a given low voltage in accordance with a pair of output stage control signals output from the input stage circuit.

Display device and driving circuit for display device

In an output mode, an output switch (SW) is turned on and supply switches (SW, SW) are turned off, and output current is supplied to an intermediate node (nc) from driving transistors (T, T). In a transition mode, the output switch (SW) is turned off and the supply switches (SW, SW) are turned on, and supply of the output current from the driving transistors (T, T) is shut off. Meanwhile, capacitance elements (C, C) receive voltage from reference nodes (Vcc, Vss). Also input voltage (Vin) is supplied to the intermediate node (nc).

Display driver circuit

A CR oscillation circuit comprises first and second logic elements, a capacitive element, and a resistive element. The first logic element is connected between a first node and a second node. The second logic element is connected between the second node and a third node. The capacitive element is connected between the first node and the second node. The resistive element is connected between the first node and the third node. The capacitive element includes a well, a diffusion layer, a gate electrode and a gate oxide film. The capacitive element has a voltage-dependence characteristic such that its capacitance value varies according to the variation in a supply voltage. The capacitance value of the capacitive element decreases when the on-resistance of the first and second logic elements increases according to the variation in the supply voltage.

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Osaka, Japan

Junji Takiguchi