Apple Inc.

Intel Corporation

Sun Microsystems, Inc.

Junji Sugisawa

Muge Wang

Suk Hwan Lim

Sung Hee Park

Kaushik Roy

Daniel C Murray

Michael Yimin Zhang

Wei-Han Lien

David J Greenhill

Joseph Raymond Siegel

Larry Kan

Dinesh Somasekhar

Dilip Lalwani

Georgios I Stamoulis

Jean Claude Cornet

Embodiments relate to a normalized cross correlation (NCC) circuit that can perform a normalized cross correlation between input patch data and kernel data. An interface circuit of an image signal processor receives input patch data from a source. Input patch data is data that represents a portion of a frame of image data from the source. The NCC circuit includes a filtering circuit and a normalization circuit. The filtering circuit receives the input patch data from the interface circuit and performs a convolution on the received input patch data or processed patch data derived from the input patch data with kernel data to produce convolution output data. The normalization circuit computes a normalized score output based on the convolution output data and the kernel data. The normalized score output includes normalization scores for each location of the convolution output data.

Circuit for performing normalized cross correlation

Embodiments of the present disclosure relate to a configurable convolution engine that receives configuration information to perform convolution or its variant operations on streaming input data of various formats. To process streaming input data, input data of multiple channels are received and stored in an input buffer circuit in an interleaved manner. Data values of the interleaved input data are retrieved and forwarded to multiplier circuits where multiplication with a corresponding filter element of a kernel is performed. Varying number of kernels with different sizes and sparsity can also be used for the convolution operations.

Configurable convolution engine

Embodiments relate to a configurable convolution engine that receives configuration information to perform convolution and other deep machine learning operations on streaming input data of various formats. The convolution engine may include two convolution circuits that each generate a stream of values by applying convolution kernels to input data. The stream of values may each define one or more channels of image data. A channel merge circuit combines the streams of values from each convolution circuit in accordance with a selected mode of operation. In one mode, the first and second streams from the convolution circuits are merged into an output stream having the combined channels of the first and second streams in an interleaved manner. In another mode, the first stream from the first convolution circuit is fed into the input of the second convolution circuit.

Configurable convolution engine for interleaved channel data

A multiplier for performing multiple types of multiplication including integer, floating point, vector, and polynomial multiplication. The multiplier includes a modified booth encoder within the multiplier and unified circuitry to perform the various types of multiplication. A carry save adder tree is modified to route sum outputs to one part of the tree and to route carry outputs to another part of the tree. The carry save adder tree is also organized into multiple carry save adder trees to perform vector multiplication.

Shared integer, floating point, polynomial, and vector multiplier

In one embodiment, a processor comprises a plurality of storage locations, a decode circuit, and a status/control register (SCR). Each storage location is addressable as a speculative register and is configured to store result data generated during execution of an instruction operation and a value representing an update for the SCR. The value includes at least a first encoding that represents an update to a plurality of bits in the SCR, and a first number of bits in the plurality of bits is greater than a second number of bits in the first encoding. The decode circuit is coupled to receive the first encoding from a first storage location responsive to retirement of a first instruction operation assigned to use the first storage location as a destination, and is configured to decode the first encoding and generate the plurality of bits. The decode circuit is configured to update the SCR.

Floating point status/control register encodings for speculative register field

A scannable latch for use within a circuit path of a series of one or more dynamic circuits is provided. The scannable latch provides both latch functionality during normal operation and scan test functionality during scan mode operation. Particularly, the scannable latch has a dynamic input stage and a shadow latch, where the dynamic input stage's primary function occurs during normal operations and where the shadow latch's primary function occurs during scan operations. The scannable latch also has an output gate operatively connected to the dynamic input stage and shadow latch.

Scannable latch for a dynamic circuit

A differential current switch logic (DCSL) system is provided which has an evaluation tree including a plurality of input terminals and a pair of complementary output nodes. The DCSL system also has an output network which establishes a pair of state outputs at a predetermined level during a precharge phase and establishes the state outputs at complementary levels in response to the evaluation tree output nodes during an evaluate phase. First and second NMOS transistors are connected in series between the DCVS output state network and the evaluation tree output nodes with their gates coupled to the state outputs to isolate the outputs from the evaluation tree following evaluation.

Differential current switch logic gate

A method and apparatus for low power transmission of digital data. A low power data transmission circuit includes a pass gate having parallel-connected n and p-channel CMOS transistors that transmit input data. To reduce power in a first embodiment, a circuit disables the parallel-connected p-channel pass gate transistor except when the input data is high (logical 1). The p-channel pass gate transistor is needed to pass logical 1's without degradation. In the first embodiment, the n-channel pass gate transistor is enabled to transmit the input data on every clock cycle. In a second embodiment, the circuit disables the parallel-connected n-channel pass gate transistor except when the input data is low (logical 0). The n-channel pass gate transistor is needed to pass logical 0's without degradation. In this embodiment, the p-channel pass gate transistor is enabled to transmit the input data on every clock cycle. These low power data transmission circuits achieve substantial power savings by avoiding unnecessary charging and discharging of the pass gate transistors' gate capacitance on every clock cycle.

Method and apparatus for low power data transmission

A data latch circuit which drives an output node to a certain value without waiting for a transition at the internal latching device. The advantage is low power consumption and high performance characteristics. The difference between a conventional differential latch and a boosted differential latch is the existence of a boosting transistor device, which allows the low power advantages of the differential latch, while improving the performance.

Boosted differential latch

The present disclosure describes a scan latch which utilizes dynamic interface nodes to facilitate full scan operation with a reduced number of transistors. A scan latch slave stage is coupled to a storage node of a storage device to capture data from that device. The scan latch slave device has an output driver with an input node coupled by a pass gate to the storage node. A scan clock line is coupled to the pass gate and to an enable input of the output driver. A slave scan clock signal received on the scan clock line enables the output driver and controls the pass gate. A master stage which may be utilized with the scan latch slave stage has a tri-state input device coupled to a serial input. The tri-state input device is controlled by a master scan clock and has an output coupled to the storage node.

Growing community of inventors

Santa Clara, CA, United States of America

Junji Sugisawa