Fujitsu Corporation

Pfu Limited

Junji Nishioka

Hirohide Sugahara

Akira Kabemoto

Toshiyuki Muta

Takatsugu Sasaki

Yozo Nakayama

Takayuki Shimamura

Jun Sakurai

Satoshi Shinohara

Naohiro Shibata

Takeshi Horie

Toshiyuki Shimizu

Hiroaki Ishihata

A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

Multiprocessor, memory accessing method for multiprocessor, transmitter

A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

Coherence apparatus for cache of multiprocessor

Growing community of inventors

Kawasaki, Japan

Junji Nishioka