Kabushiki Kaisha Toshiba

Mitsubishi Denki Kabushiki Kaisha

Toshiba Energy Systems & Solutions Corporation

Junji Mori

Takashi Fujita

Yoshihiro Fujita

Takeshi Yoshida

Mitsuo Saito

Itaru Yamazaki

Yoshihisa Kondo

Nobuhiro Ide

Masahiko Nakazono

Masato Nagamatsu

Toshiaki Suzuki

Takayuki Miyamoto

Takeshi Aikawa

Ryuta Hasegawa

Toru Kubo

Teruyuki Ishizuki

Kiyoshi Kusunoki

Takahisa Kageyama

Takashi Tatsumi

Harutaka Goto

Yuichi Shiozaki

Hiroki Sugano

Terumasa Nagasaki

Tomoaki Ohashi

Ryoji Hakataya

Kenichi Imamura

Shoji Iida

Oki Osada

Hiroyuki Okawa

Takeyoshi Asano

Kouya Inada

Satsumi Ishikawa

Hiroya Nakano

Takashisa Kageyama

A movable-blade operation system for a hydraulic machine according to an embodiment includes an oil hydraulic cylinder installed within a rotational shaft, a bidirectional pump, a pump drive motor, a control unit, and an oil head installed in the hydraulic machine. The bidirectional pump selectively feeds pressurized hydraulic oil to one of a first cylinder chamber and a second cylinder chamber. The oil head couples the rotational shaft rotatably, and the hydraulic oil fed from the bidirectional pump to the first cylinder chamber and the second cylinder chamber flows through the oil head. The bidirectional pump, the pump drive motor, and the control unit are installed outside the hydraulic machine.

Movable-blade operation system for hydraulic machine

According to one embodiment, a pumped-storage power generation control device includes a control section that controls at least one of the pumping input of the pumped-storage power generation facility in the pumping operation and the power output of the pumped-storage power generation facility in the power generating operation such that a value, which is obtained by a predetermined calculation using the measurement value relating to the pumping input of the pumped-storage power generation facility in the pumping operation and the measurement value relating to the power output of the pumped-storage power generation facility in the power generating operation, becomes a set target value.

Pumped-storage power generation control device and pumped-storage power generation control method

According to one embodiment, there is provided a variable-speed operation control apparatus of a hydroelectric power generation system including a power generator interconnected to a power system through a main circuit and a water turbine directly connected to the power generator. The apparatus includes a branch circuit branched from the main circuit and including a frequency converter which performs conversion between an output frequency of the power generator and a system frequency of the power system, wherein the power generator is interconnected to the power system through the branch circuit when a flow rate of water is less than a fixed level.

Variable-speed operation control apparatus and hydroelectric power generation system

A first storage unit stores an address of a branching instruction and a branched address. A first detector detects whether or not an instruction of the present address has previously been branched from an output of the first storage unit. When the first detector detects previous branching of the instruction of the present address, the second storage unit stores the branched address corresponding to the address of the instruction to be executed following the branching instruction. When a second detector detects an output of a program counter as the address of the instruction to be executed following the branching instruction, the second storage unit outputs the branched address.

Multi-table branch prediction circuit for predicting a branch's target address based on the branch's delay slot instruction address

A semiconductor integrated circuit device includes a semiconductor memory circuit device, a first sequencer, and a second sequencer. The semiconductor memory circuit device stores data. The first sequencer controls writing of data into the semiconductor memory circuit device. The second sequencer controls reading of data from the semiconductor memory circuit device.

Semiconductor integrated circuit device equipped with read sequencer and write sequencer

The semiconductor circuit includes a driver that is input with a signal, a driver that is input with a signal, and a driver of which input terminal is connected to output terminals of both the drivers, and of which output terminal is connected to input terminals of both the drivers.

Semiconductor circuit and semiconductor device

A test facilitating circuit of a microprocessor has a mode register (11). If data stored in the mode register indicates a test mode, the test facilitating circuit uses a test mode function of a cache memory (1), to execute a test program written in the cache memory irrespective of the resetting of the microprocessor. The test program carries out a built-in test on internal circuits of the microprocessor. Results of the test are stored in the cache memory. After the test, an external tester reads the test results out of the cache memory and examines them.

Test facilitating circuit of microprocessor

Disclosed is a pipeline information processing circuit which comprises a register control unit for outputting a plurality of data held in registers at a time; an arithmetic operation unit for carrying out a collective arithmetic operation of a plurality of data; and a bypass control unit for comparing an operation result outputted from the arithmetic operation unit and a data outputted from the register control unit, selecting a data to be an object of the next arithmetic operation, and transferring the selected data to the arithmetic operation unit through a suitable bypass.

Pipeline information processing circuit for floating point operations

The branch prediction device of this invention is for use in a pipeline processor where a plurality of instructions are simultaneously processed in various stages, such as the fetch stage, execution stage, memory access stage and register write stage. A two-port branch prediction buffer enables simultaneous operation of the registration and retrieval processes so that a previously registered address can be obtained during the same clock pulse as registration of another branch address occurs.

Branch prediction device enabling simultaneous access to a

The branch prediction using a branch prediction table formed by an associative memory which is applicable to a super scalar processor without causing confusion in the branch prediction. The branch prediction uses a branch prediction table for registering entries, each entry including a branching address, a branch target address, and an instruction position indicating a position of the predicted branch instruction in group of instructions to be executed concurrently, or an entry address indicating a position of each entry in the associative memory of the table. A correctness of the predicted branch instruction is checked by using actual branch target address and/or actual instruction position of actual branch instruction encountered in the actual execution of presently fetched instructions. When the predicted branch instruction is incorrect, instructions fetched at a next processing timing are invalidated and the entry in the table is rewritten.

Method and apparatus for branch prediction using branch prediction table

In a serial memory, data signal holding circuits for temporarily holding data read from memory cells are provided as a data register. One holding circuit includes a latch circuit and capacitors connected to input/output nodes of the latch circuit, respectively. The capacitors contribute to stabilizing the latch function by the latch circuit. Therefore, when transistors turn on in response to a serial selection signal at a high level, the latch circuit is prevented from being inverted by the potentials of a serial bus line pair. Accordingly, generation of reading errors is prevented.

Semiconductor memory device capable of correctly and serially reading

A floating-point division cell consisting of partial remainder data register for storing parallel-partial-remainder data or third partial remainder data, divisor data register for storing parallel-divisor data or third divisor data, low-order divisor data generator for receiving the low-order portion of the divisor data and generating low-order divisor data, low-order partial remainder calculator for obtaining low-order multi-divisor data by multiplying the low-order divisor data and a multiple of 2 together and calculating new low-order partial remainder data by subtracting or adding the low-order multi-divisor data from/to the low-order portion of the partial remainder data, high-order divisor data generator for receiving the high-order portion of the divisor data and generating high-order divisor data, and high-order partial remainder calculator for obtaining high-order multi-divisor data by multiplying the high-order divisor data and a multiple of 2 together and calculating new high-order partial remainder data by subtracting or adding the high-order multi-divisor data from/to the high-order portion of the partial remainder data.

Floating-point division cell

A division circuit having a plurality of stages based on a repeat arithmetic operation method, with each stage having: a constant multiplier for multiplying a divisor by a predetermined constant multiple; a carry save type adder (CSA) for performing an addition operation between a dividend and the constant multiple value of the divisor provided from the constant multiplier, then for outputting a sum component and a carry component as a result of the addition operation; shifters for shifting the sum component and the carry component by a shift amount in accordance with a radix, respectively; a carry propagation adder (CPA) for performing an addition operation between the upper bits of the shifted sum component and the shifted carry component obtained by the shifter by predetermined bits; and comparators for outputting a part of a quotient having a plurality of bits by comparing the result obtained by the CPA and the constant multiple value of the divisor, then for determining the value of the constant multiple of the constant multiplier based on the comparison result. In the division circuit, the value of the constant multiple at the following constant multiplier is determined by the output of the comparator and the output of the CPA, the sum component and the carry component obtained by the CSA are provided to a CSA in the following stage, and the dividend and zero in place of the sum component and the carry component are input to the CSA in the first stage.

Division circuit using higher radices

A dividend or partial remainder is stored in a partial remainder register. An output of the partial remainder register is shifted to the left by a radix which uses the power of 2 and is larger than 2. A divisor is stored in a divisor register. Comparison constants obtained by subjecting an output of the divisor register to predetermined operations are stored in comparison constant registers. Subtracters respectively receive outputs of the comparison constant registers as one input, receive upper bits of a bit number representing a precision required for conversion and included in the output of the partial remainder shifter as another input, and compare the magnitudes of the two inputs with each other to derive partial quotients. A selector shifts and selects an output of the divisor register according to the signs of the remainder quotients output from the subtracters to create a factor having a value equal to the integer multiple of the divisor. An adder/subtracter receives an output of the selector and an output of the partial remainder shifter and the addition or subtraction of the adder/subtracter is selectively specified by the sign bit of an output of the partial remainder shifter to derive a partial remainder.

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Tokyo, Japan

Junji Mori